Methods and structures of integrated MEMS-CMOS devices

Patent metadata

Field	Value
Publication number	US-9950924-B2
Application number	US-201514985388-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Mar 9, 2012
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

First claim

What is claimed is:

1. A method for fabricating an integrated MEMS-CMOS device comprising:
providing a substrate having a surface region;
forming a CMOS IC layer overlying the surface region, the CMOS IC layer having at least one CMOS electrode coupled to an ESD diode;
forming a mechanical structural layer overlying the CMOS IC layer;
forming at least one MEMS device overlying the CMOS IC layer from a first portion of the mechanical structural layer, the at least one MEMS devices having at least one MEMS electrode;
forming a protection structure from a second portion of the mechanical structural layer, the protection structure including one or more ground posts and a jumper, wherein the protection structure is coupled to the at least one MEMS electrode and the at least one CMOS electrode through the jumper, wherein the protection structure is configured to couple the CMOS electrode to electrical ground through the one or more ground posts; and
etching the mechanical structural layer to separate the one or more ground posts from the jumper, wherein the CMOS electrode is connected to the electrical ground until the mechanical structural layer is completely etched.

2. The method of claim 1 wherein the ESD diode is coupled to the at least one CMOS electrode.

3. The method of claim 1 wherein the jumper is coupled the at least one MEMS electrode and the at least one CMOS electrode.

4. The method of claim 3 wherein the at least one MEMS electrode and the at least one CMOS electrode are electrically coupled via the jumper after the forming of the at least one MEMS device.

5. The method of claim 1 further comprising forming an electrode ground ring structure overlying the at least one CMOS device, the electrode ground ring structure being coupled to ground and the at least one CMOS device.

6. The method of claim 5 wherein the electrode ground ring structure is configured to direct plasma induced charge from a plasma etching process to ground.

7. The method of claim 1 wherein the forming of the mechanical structural layer, the at least one MEMS device, and the protection structure comprises a plasma etching process.

8. The method of claim 1 wherein the protection structure is configured to direct plasma induced charge from a plasma etching process to ground.

9. The method of claim 1 wherein the one or more MEMS devices comprises an inertial sensor, an accelerometer, a gyrometer, a magnetic field sensor, a pressure sensor, a humidity sensor, a temperature sensor, a chemical sensor, or a biosensor.

Assignees

• Mcube Inc

Inventors

• Sridharamurthy Sudheer S
• Lee Te-Hse Terrence
• Rastegar Ali J
• Stancu Mugurel
• Yang Xiao Charles

Classifications

• B81B2207/094

  Feed-through, via · CPC title

• B81B7/0022

  Protection against electrostatic discharge (circuit arrangements for protecting electronic switching circuits used for pulse technique against overcurrent or overvoltage H03K17/08; electrostatic discharge protection for electronic semiconductor circuits H10D89/60) · CPC title

• B81C2201/0132

  Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling · CPC title

• B81C1/00238

  Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

• B81C2201/05

  Temporary protection of devices or parts of the devices during manufacturing · CPC title