Capacitor with planarized bonding for cmos-mems integration
US-2016031704-A1 · Feb 4, 2016 · US
CMOS-MEMS integrated device with selective bond pad protection
US9505609B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9505609-B2 |
| Application number | US-201514699938-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 29, 2015 |
| Priority date | Apr 29, 2015 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for preparing a semiconductor wafer, the method comprising: providing a passivation layer over a patterned top metal on the semiconductor wafer; etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask; depositing a protection layer on the semiconductor wafer; patterning the protection layer using a second mask; further etching the passivation layer to open other electrodes in the semiconductor wafer usi…
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Classifications
- H10W72/0198Primary
Electricity · mapped topic
Electricity · mapped topic
- B81C1/00238Primary
Operations & Transport · mapped topic
Operations & Transport · mapped topic
- B81C1/00801Primary
Operations & Transport · mapped topic
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Frequently asked questions
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- What does patent US9505609B2 cover?
- A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second …
- Who is the assignee on this patent?
- Invensense Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W72/0198. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).