Methods and Structures of Integrated MEMS-CMOS Devices

US2016176708A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016176708-A1
Application numberUS-201514985388-A
CountryUS
Kind codeA1
Filing dateDec 30, 2015
Priority dateMar 9, 2012
Publication dateJun 23, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

First claim

Opening claim text (preview).

1 - 11 . (canceled) 12 . A method for fabricating an integrated MEMS-CMOS device comprising: providing a substrate having a surface region; forming a CMOS IC layer overlying the surface region, the CMOS IC layer having at least one CMOS electrode; forming a mechanical structural layer overlying the CMOS IC layer; forming at least one MEMS device overlying the CMOS IC layer from a first portion of the mechanical structural layer, the at least one MEMS devices having at least one MEMS electrode; and forming a protection structure from a second portion of the mechanical structural layer, the protection structure including one or more ground posts, a jumper, and an ESD diode, wherein the protection structure is coupled to the at least one MEMS electrode and the at least one CMOS electrode. 13 . The method of claim 12 wherein the ESD diode is coupled to the at least one CMOS electrode. 14 . The method of claim 12 wherein the jumper is coupled the at least one MEMS electrode and the at least one CMOS electrode. 15 . The method of claim 14 wherein the at least one MEMS electrode and the at least one CMOS electrode are electrically coupled via the jumper after the forming of the at least one MEMS device. 16 . The method of claim 12 further comprising forming an electrode ground ring structure overlying the at least one CMOS device, the electrode ground ring structure being coupled to ground and the at least one CMOS device. 17 . The method of claim 16 wherein the electrode ground ring structure is configured to direct plasma induced charge from a plasma etching process to ground. 18 . The method of claim 12 wherein the forming of the mechanical structural layer, the at least one MEMS device, and the protection structure comprises a plasma etching process. 19 . The method of claim 12 wherein the protection structure is configured to direct plasma induced charge from a plasma etching process to ground. 20 . The method of claim 12 wherein the one or more MEMS devices comprises an inertial sensor, an accelerometer, a gyrometer, a magnetic field sensor, a pressure sensor, a humidity sensor, a temperature sensor, a chemical sensor, or a biosensor. 21 . A method for fabricating an integrated MEMS-CMOS device comprising: providing a substrate having a surface region; forming a CMOS IC layer overlying the surface region, the CMOS IC layer having at least one CMOS electrode; forming a mechanical structural layer overlying the CMOS IC layer, the mechanical structural layer including an electrically conductive mechanical structural layer that includes a first via coupled to the CMOS electrode, a second via coupled to a MEMS electrode, and one or more vias coupled to ground; and forming at least one MEMS device overlying the CMOS IC layer from a portion of the mechanical structural layer, the at least one MEMS devices coupled to the MEMS electrode; wherein the forming of the at least one MEMS device includes a plasma etching process that removes a portion of the electrically conductive mechanical structural layer to electrically separate the first via and the second via from the ground and maintain coupling between the first via and the second via to form a jumper for coupling the CMOS electrode and the MEMS electrode. 22 . The method of claim 21 comprising forming an ESD diode coupled to the at least one CMOS electrode. 23 . The device of claim 21 further comprising an electrode ground ring structure overlying the at least one CMOS device, the electrode ground ring structure being coupled to ground and the at least one CMOS device. 24 . The method of claim 21 wherein the at least one MEMS electrode and the at least one CMOS electrode are electrically coupled via the jumper after the forming of the at least one MEMS device. 25 . The method of claim 21 wherein the electrically conductive mechanical structural layer is configured to direct plasma induced charge from a plasma etching process to ground. 26 . The method of claim 21 wherein the one or more MEMS devices comprises an inertial sensor, an accelerometer, a gyrometer, a magnetic field sensor, a pressure sensor, a humidity sensor, a temperature sensor, a chemical sensor, or a biosensor. 27 . An integrated MEMS-CMOS device, comprising: a CMOS IC layer overlying a surface region of a substrate, the CMOS IC layer having at least one CMOS electrode; at least one MEMS device a mechanical structural layer overlying the CMOS IC layer, the at least one MEMS devices coupled to a MEMS electrode; an electrically conductive mechanical structural layer overlying the CMOS IC layer, the electrically conductive mechanical structural layer including a first via coupled to a second via, the first via coupled to the CMOS electrode and the second via coupled to the MEMS electrode, the electrically conductive mechanical structural layer further includes one or more ground vias coupled to ground, the ground vias being electrically uncoupled to the first and second vias. 28 . The device of claim 27 , further comprising an ESD diode structure coupled to the at least one CMOS electrode. 29 . The device of claim 28 , wherein the ESD diode structure comprises a first diode coupling the at least one CMOS electrode to a power supply terminal and a first diode coupling the at least one CMOS electrode to a ground terminal. 30 . The device of claim 27 , further comprising an electrode ground ring structure overlying the at least one CMOS device, the electrode ground ring structure being coupled to ground and the at least one CMOS device 31 . The device of claim 27 , wherein the one or more MEMS devices comprises an inertial sensor, an accelerometer, a gyrometer, a magnetic field sensor, a pressure sensor, a humidity sensor, a temperature sensor, a chemical sensor, or a biosensor.

Assignees

Inventors

Classifications

  • Temporary protection of devices or parts of the devices during manufacturing · CPC title

  • Feed-through, via · CPC title

  • for protecting against electromagnetic or electrostatic interferences · CPC title

  • Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling · CPC title

  • Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

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What does patent US2016176708A1 cover?
A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS device…
Who is the assignee on this patent?
Mcube Inc
What technology area does this patent fall under?
Primary CPC classification B81C1/00801. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Thu Jun 23 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).