Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices

Patent metadata

Field	Value
Publication number	US-9487396-B2
Application number	US-201414477451-A
Country	US
Kind code	B2
Filing date	Sep 4, 2014
Priority date	Sep 4, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

First claim

What is claimed is:

1. A device, comprising:
an integrated circuit substrate comprising a passivation opening having a sidewall that exposes a portion of a dielectric layer of the integrated circuit substrate;
a first barrier layer deposited on the sidewall that prohibits exposure of the dielectric layer to a release chemical employable to release a micro-electro-mechanical (MEMS) device integrated with the integrated circuit substrate, wherein the first barrier layer comprises a metal; and
a second barrier layer comprising an electrically insulating layer disposed directly over a part of the first barrier layer that covers the portion of the dielectric layer that is exposed, wherein the second barrier layer is at least partially resistant to the release chemical, and
wherein the first barrier layer is disposed between the second barrier layer and the dielectric layer.

2. The device of claim 1 , wherein the passivation opening exposes a metal pad of the integrated circuit substrate.

3. The device of claim 2 , wherein the passivation opening facilitates a bonding that bonds the integrated circuit substrate to the MEMS device via the metal pad, wherein the bonding comprises at least one of an eutectic bonding, metal compression bonding, fusion bonding, anodic bonding, or copper-to-copper bonding.

4. The device of claim 2 , wherein the passivation opening exposes a wire-bond pad to facilitate packaging the device.

5. The device of claim 2 , wherein the passivation opening exposes a probe pad.

6. The device of claim 1 , wherein the integrated circuit substrate comprises a complementary metal-oxide-semiconductor (CMOS) layer.

7. The device of claim 1 , wherein the first barrier layer is comprised of at least one of Aluminum, Aluminum-Copper, Titanium, or Titanium Nitride.

8. The device of claim 1 , wherein the release chemical comprises at least one of vapor-phase hydrofluoric acid or liquid-phase hydrofluoric acid.

9. The device of claim 1 , wherein the first barrier layer is deposited on the sidewall via at least one of a sputtering, evaporation, atomic layer deposition, plasma enhanced chemical vapor deposition, or low pressure chemical vapor deposition process.

10. The device of claim 1 , wherein the MEMS device is fabricated within the integrated circuit substrate.

11. The device of claim 1 , wherein the second barrier layer is deposited on the portion of the first barrier layer via at least one of a sputtering, evaporation, atomic layer deposition, plasma enhanced chemical vapor deposition, or low pressure chemical vapor deposition process.

12. The device of claim 1 , wherein the dielectric layer comprises at least one of a silicon oxide layer or a silicon nitride layer.

Assignees

• Invensense Inc

Inventors

• Daneman Michael J
• Assaderaghi Fariborz

Classifications

• B81C1/00539

  Wet etching · CPC title

• B81B2207/015

  the micromechanical device and the control or processing electronics being integrated on the same substrate · CPC title

• B81C2203/0735

  Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit · CPC title

• B81C1/00801 Primary

  Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer (B81C1/00595, B81C1/00468 take precedence) · CPC title

• B81B7/0025

  Protection against chemical alteration · CPC title