3D stacked non-volatile storage programming to conductive state

Patent metadata

Field	Value
Publication number	US-9099202-B2
Application number	US-201213670233-A
Country	US
Kind code	B2
Filing date	Nov 6, 2012
Priority date	Nov 6, 2012
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

Programming NAND strings in a 3D stacked storage device to a conductive state. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided.

First claim

What is claimed is:

1. A method of operating 3D stacked non-volatile storage comprising a plurality of word lines comprising conductive material that is oriented horizontally, the conductive material alternates with dielectric material in a stack, and a plurality of NAND strings that are oriented vertically, the method comprising:
erasing a group of non-volatile storage elements associated with a set of NAND strings of the plurality of NAND strings to an erase threshold voltage distribution above zero volts; and
programming selected non-volatile storage elements in the group by reducing the threshold voltage of the selected non-volatile storage elements, including establishing a programming voltage in channels associated with selected NAND strings of the set of NAND strings, wherein the programming selected non-volatile storage elements further comprises applying a sequence of voltages to a selected word line associated with the selected NAND strings, and applying a voltage to a first bit line associated with a first selected NAND string of the selected NAND strings that increases in magnitude with later voltages in the sequence of voltages applied to the selected word line until a first of the selected non-volatile storage elements that is on the first selected NAND string is programmed.

2. The method of claim 1 , wherein each voltage in the sequence of voltages applied to the selected word line is lower than the voltage applied to the first bit line.

3. The method of claim 1 , further comprising:
applying an inhibit voltage to an unselected bit line that is associated with an unselected NAND string of the set of NAND strings;
applying a voltage to a drain select gate associated with the unselected NAND string to pass the inhibit voltage to a channel of the unselected NAND string; and
applying a voltage to an unselected word line associated with the unselected NAND string to prevent programming of a non-volatile storage element on the unselected NAND string.

4. The method of claim 1 ,
wherein the establishing a programming voltage in channels associated with selected NAND strings of the set of NAND strings includes applying the programming voltage to selected bit lines associated with the selected NAND strings while applying a voltage to select gates of the selected NAND strings to pass the programming voltage to channels of the selected NAND strings; and
wherein the applying a sequence of voltages to a selected word line associated with the selected NAND strings includes applying a voltage to the selected word line while the programming voltage is in the channels of the selected NAND strings to program the first selected non-volatile storage element that is on the first selected NAND string.

5. The method of claim 4 , wherein the programming selected non-volatile storage elements further includes:
applying a first voltage to an unselected word line associated with the first selected NAND string while the programming voltage is in the channel of the first selected NAND string that prevents programming of a non-volatile storage element on the first selected NAND string that has already been programmed; and
applying a second voltage to any unselected word lines associated with the first selected NAND string that are between the selected word line and the bit line of the first selected NAND string while the programming voltage is in the channel of the first selected NAND string, the second voltage allows the programming voltage to pass to a channel of the first selected non-volatile storage element.

6. The method of claim 5 , wherein the set of NAND strings are in a first block that is selected for programming, the plurality of NAND strings includes a set in a second block, each NAND string in the second block comprising a drain side select gate at a first end of each NAND string, the drain side select gate of the NAND strings in the second block including a first transistor and a second transistor, the first transistor is closer to a bit line associated with the NAND string than the second transistor, a first NAND string in the second block shares a bit line with the first selected NAND string in the first block, and further comprising:
applying a voltage that is equal to the programming voltage to the first transistor of drain side select gates of NAND strings in the second block;
applying an inhibit voltage to the second transistor of drain side select gates of NAND strings in the second block; and
applying the inhibit voltage to all word lines in the second block.

7. A 3D stacked non-volatile memory device, comprising:
a substrate;
a plurality of word lines comprising conductive material that is oriented horizontally with respect to the substrate, the conductive material alternates with dielectric material in a stack;
a plurality of NAND strings that are oriented vertically with respect to the substrate, each NAND string comprising a set of non-volatile storage elements and a drain side select gate at a first end of each NAND string;
a plurality of bit lines, each bit line coupled to the drain side select gate of one of the NAND strings; and
one or more managing circuits in communication with the plurality of word lines, the plurality of bit lines, and the plurality of NAND strings, the one or more managing circuits are configured to erase non-volatile storage elements of a set of NAND strings of the plurality of NAND strings to an erase threshold distribution above zero volts, the one or more managing circuits are configured to program selected non-volatile storage elements of the set of NAND strings by reducing threshold voltages of the selected non-volatile storage elements below the erase threshold distribution, including establishing a programming voltage in channels associated with selected NAND strings of the set of NAND strings, wherein the one or more managing circuits being configured to program the selected non-volatile storage elements comprises the one or more managing circuits being configured to apply a sequence of voltages to a selected word line associated with the selected NAND strings and configured to apply a voltage to bit lines associated with the selected NAND strings that increases with later voltages in the sequence until a first of the selected non-volatile storage elements that is on a first of the selected NAND string is programmed.

8. The 3D stacked non-volatile memory device of claim 7 , wherein each voltage in the sequence of voltages applied to the selected word line is lower than the voltage applied to the bit lines associated with the selected NAND strings.

9. The 3D stacked non-volatile memory device of claim 7 , wherein the one or more managing circuits are further configured to apply an inhibit voltage to an unselected bit line that is associated with an unselected NAND string of the set of NAND strings, the one or more managing circuits are further configured to apply a voltage to a drain select gate associated with the unselected NAND string to pass the inhibit voltage to a channel of the unselected NAND string, the one or more managing circuits are further configured to apply a voltage to an unselected word line associated with the unselected NAND string to prevent programming of a non-volatile storage element on the unselected NAND string.

10. The 3D stacked non-volatile memory device of claim 7 , wherein the one or more managing circuits being configured to establish the programming voltage in the channels associated with the selected NAND strings comprises the one or more managing circuits being configured to apply a voltage to drain side select gates of the selected NAND strings while the one or more managing circuits apply the voltage to the bit lines associated wi

Assignees

• Sandisk Technologies Inc

Inventors

• Mihnea Andrei
• Costa Xiying
• Zhang Yanli

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5671 Primary

  using charge trapping in an insulator · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic