Semiconductor device and methods of manufacturing and operating the same

Patent metadata

Field	Value
Publication number	US-9053796-B2
Application number	US-201414198064-A
Country	US
Kind code	B2
Filing date	Mar 5, 2014
Priority date	Oct 24, 2013
Publication date	Jun 9, 2015
Grant date	Jun 9, 2015

Abstract

A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel layer;
a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and
a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.

2. The semiconductor device of claim 1 , wherein, when the program operation on the plurality of selection transistors is performed, the control circuit applies a program allowance voltage or a program prohibition voltage to bit lines corresponding to the vertical channel layer, applies the pass voltage to the two or more selection lines and the word lines, applies the program voltage to the two or more selection lines while controlling the peripheral circuit to decrease the pass voltage applied to the word line adjacent to the two or more selection lines, among the word lines.

3. The semiconductor device of claim 2 , wherein the control circuit controls the peripheral circuit to lower the pass voltage applied to the word line adjacent to the two or more selection lines to a voltage that is higher than a ground voltage.

4. The semiconductor device of claim 2 , wherein the control circuit controls the peripheral circuit to maintain the pass voltage applied to the other word lines while lowering the pass voltage applied to the word line adjacent to the two or more selection lines.

5. A method of operating a semiconductor device with a plurality memory cells and two or more selection transistors formed along a vertical channel, the method comprising:
applying a pass voltage to selection lines connected to the two or more selection transistors and a plurality word lines connected to the memory cells to program the two or more selection transistors;
applying a program voltage to the two or more selection lines;
lowering the pass voltage applied to a word line adjacent to the selection lines among the word lines when applying the program voltage to the two or more selection lines; and
discharging the two or more selection lines and the word lines.

6. The method of claim 5 , further comprising, before the applying of the pass voltage, applying a program allowance voltage or a program prohibition voltage to a bit line corresponding to the vertical channel layer.

7. The method of claim 5 , wherein the lowering of the pass voltage lowers the pass voltage to a voltage that is higher than a ground voltage.

8. The method of claim 5 , wherein the lowering of the pass voltage maintains the pass voltage applied to the other word lines.

9. The method of claim 5 , further comprising, between the lowering of the pass voltage and the discharging of the two or more selection lines and the word lines, lowering a voltage applied to the two or more selection lines to the pass voltage.

Assignees

• Sk Hynix Inc

Inventors

• Shim Keon Soo

Classifications

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• H01L27/11551

  Electricity · mapped topic

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title