Read-only memory (ROM) device structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-9941290-B2
Application number	US-201615261282-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Jun 1, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A read-only memory (ROM) structure is provided. The ROM device structure includes an active region formed over a substrate and a first group of word lines formed over the active region. The first group of word lines includes at least two word lines. The ROM device structure includes a second group of word lines formed on the active region, and the second group of word lines includes at least two word lines. The ROM device structure further includes an isolation line between the first group of word lines and the second group of word lines and over the active region. The first group of word lines, the second group of word lines, and the isolation line are formed in a second metal layer.

First claim

What is claimed is:

1. A read-only memory (ROM) device structure, comprising:
an active region over a substrate, wherein the active region comprises a first bit-cell region and a second bit cell region;
a first gate structure formed over the active region in the first bit-cell region, wherein the first gate structure comprises a first work function layer with a first thickness;
a second gate structure formed over the active region in the second bit-cell region, wherein the second gate structure comprises the first work function layer with the first thickness;
an isolation structure formed over the active region, wherein the isolation structure is between the first gate structure and the second gate structure, wherein the isolation structure comprises a second work function layer with a second thickness, and the second thickness is larger than or smaller than the first thickness;
a first contact structure formed over the active region in the first bit-cell region, wherein the first contact structure is between the first gate structure and the isolation structure.

2. The read-only memory (ROM) device structure as claimed in claim 1 , further comprising:
an interconnect structure formed over the first gate structure, the second gate structure and the isolation structure, wherein the interconnect structure comprises:
a first metal layer formed over the first gate structure, wherein the first contact structure is electrically connected to the first metal layer; and
a second metal layer formed over the first metal layer, wherein the first gate structure is electrically connected to the second metal layer.

3. The read-only memory (ROM) device structure as claimed in claim 1 , wherein the first work function layer has a first-type conductivity, and the second work function layer has a second-type conductivity.

4. The read-only memory (ROM) device structure as claimed in claim 1 , wherein the active region is a continuous active region which is extending under the first gate structure, the second gate structure and the isolation structure.

5. The read-only memory (ROM) device structure as claimed in claim 1 , further comprising:
a second contact structure formed over the active region in the second bit-cell region, wherein the second contact structure is between the second gate structure and the isolation structure.

6. The read-only memory (ROM) device structure as claimed in claim 1 , wherein the isolation structure is electrically connected to a ground potential (GND) or a voltage supply (Vdd).

7. The read-only memory (ROM) device structure as claimed in claim 1 , wherein the first contact structure is electrically connected to a voltage supply (Vdd).

8. The read-only memory (ROM) device structure as claimed in claim 1 , wherein a top surface of the first contact structure is higher than a top surface of the first gate structure.

9. The read-only memory (ROM) device structure as claimed in claim 1 , further comprising:
a third contact structure formed over the active region, wherein the first gate structure is formed between the first contact structure and the third contact structure, the third contact structure is electrically connected to a ground potential (GND).

10. The read-only memory (ROM) device structure as claimed in claim 1 , further comprising:
a source/drain (S/D) structure formed in the active region and directly below the first contact structure, wherein the S/D structure is between the first gate structure and the second gate structure.

11. A read-only memory (ROM) device structure, comprising:
an active region over a substrate;
a first gate structure formed on the active region, wherein the first gate structure comprises a first work function layer with a first-type conductivity;
a second gate structure formed on the active region, wherein the second gate structure comprises the first work function layer with the first-type conductivity;
a first contact structure formed over the active region, wherein the first contact structure is between the first gate structure and the second gate structure;
a first isolation structure formed over the active region, wherein the first isolation structure is closer to the first gate structure than the second gate structure, and the first isolation structure comprises a second work function layer with a second-type conductivity, wherein the first-type conductivity is different from the second-type conductivity; and
a second isolation structure formed over the active region, wherein the second isolation structure is closer to the second gate structure than the first gate structure.

12. The read-only memory (ROM) device structure as claimed in claim 11 , wherein the first contact structure is electrically connected to a ground potential (GND).

13. The read-only memory (ROM) device structure as claimed in claim 11 , further comprising:
a second contact structure formed over the active region, wherein the second contact structure is between the first isolation structure and the first gate structure.

14. The read-only memory (ROM) device structure as claimed in claim 13 , wherein the second contact structure is electrically connected to a voltage supply (Vdd).

15. The read-only memory (ROM) device structure as claimed in claim 11 , wherein the first isolation structure is electrically connected to a ground potential (GND) or a voltage supply (Vdd).

16. The read-only memory (ROM) device structure as claimed in claim 11 , wherein a half portion of the first isolation structure, the first gate structure, the second gate structure and a half portion of the second isolation structure are in a bit-cell region.

17. The read-only memory (ROM) device structure as claimed in claim 11 , wherein the first work function layer has a first thickness, the second work function layer has a second thickness, the first thickness is larger than or smaller than the second thickness.

18. A read-only memory (ROM) device structure, comprising:
an active region formed over a substrate;
a first group of word lines formed over the active region, wherein the first group of word lines comprises at least two word lines;
a second group of word lines formed on the active region, wherein the second group of word lines comprises at least two word lines;
an isolation line between the first group of word lines and the second group of word lines and over the active region, wherein the first group of word lines, the second group of word lines, and the isolation line are formed in a second metal layer;
at least two gate structures formed below the first group of word lines, wherein each of the gate structures has a first work function layer with a first thickness; and
an isolation structure formed below the isolation line, wherein the isolation structure has a second work function layer with a second thickness, and the second thickness is larger than or smaller than the first thickness.

19. The read-only memory (ROM) device structure as claimed in claim 18 , further comprising:
at least two bit lines formed over the active region, wherein the bit lines are orthogonal to the word lines, and the bit lines are formed in a first metal layer below the second metal layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manufacaturing Co Ltd

Inventors

• Hsieh Chih-Hung

Classifications

• H10D64/669

  the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H01L27/092

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L27/11273 Primary

  Electricity · mapped topic