Tight pitch inverter using vertical transistors

Patent metadata

Field	Value
Publication number	US-10141309-B2
Application number	US-201715825088-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	Feb 16, 2017
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the transistors. The gate contact and the drain contact of the transistors are shared. Wiring of inverter input, output and power supply lines is simplified.

First claim

What is claimed is:

1. A fabrication method for forming an inverter structure, comprising:
obtaining a monolithic structure including a p-type region and an n-type region, the p-type region being electrically isolated from the n-type region;
forming a dummy gate on the monolithic structure;
epitaxially forming first and second semiconductor fins on the monolithic structure and within the dummy gate, the first semiconductor fin being formed on the p-type region and the second semiconductor fin being formed on the n-type region;
forming a first drain region on the first semiconductor fin and above the dummy gate, the first drain region having p-type conductivity;
forming a second drain region on the second semiconductor fin and above the dummy gate, the second drain region having n-type conductivity, and
replacing the dummy gate with a gate dielectric layer and an electrically conductive gate electrode on the gate dielectric layer such that the gate dielectric layer adjoins the first and second semiconductor fins and the gate electrode adjoins the gate dielectric layer, and further such that:
the p-type region, the first semiconductor fin, the first drain region, and the gate electrode form a vertical, p-type field-effect transistor,
the n-type region, the second semiconductor fin, the second drain region, and the gate electrode form a vertical, n-type field-effect transistor, and
the gate electrode is shared by the p-type field-effect transistor and the n-type field-effect transistor.

2. The method of claim 1 , further including:
forming an interlayer dielectric layer over the gate electrode;
forming a first trench in the interlayer dielectric layer exposing portions of the first drain region and the second drain region;
forming a drain contact within the first trench, the drain contact being shared by the first and second drain regions;
forming a second trench in the interlayer dielectric layer down to the gate electrode, and
forming a gate contact within the second trench, the gate contact being electrically connected to the gate electrode.

3. The method of claim 2 , further including:
electrically connecting the gate contact to an input line;
electrically connecting the drain contact to an output line;
electrically connecting the n-type region of the n-type field-effect transistor to a relatively low voltage power supply, and
electrically connecting the p-type region of the p-type field-effect transistor to a relatively high voltage power supply.

4. The method of claim 2 , wherein the monolithic structure further includes first and second electrically isolated, counter-doped regions adjoining the p-type region and the n-type region, respectively, further including:
forming a bottom spacer on the monolithic structure;
forming a top spacer on the dummy gate;
forming a top dielectric layer on the top spacer;
forming first and second vertical recesses extending through the top dielectric layer, the top spacer, the dummy gate, and the bottom spacer, and
further wherein epitaxially forming the first and second semiconductor fins includes forming the semiconductor fins respectively within the first and second vertical recesses.

5. The method of claim 4 , further including:
exposing a top portion of the first semiconductor fin above the top spacer;
forming the first drain region on the exposed top portion of the first semiconductor fin;
exposing a top portion of the second semiconductor fin above the top spacer;
forming the second drain region on the exposed top portion of the second semiconductor fin, and
forming the drain contact directly above the first drain region and the second drain region.

6. The method of claim 5 , further including:
reducing the width of the top portion of the first semiconductor fin;
epitaxially growing a p-type drain region to form the first drain region;
reducing the width of the top portion of the second semiconductor fin;
epitaxially growing an n-type drain region to form the second drain region, and
reducing the widths of the first and second drain regions.

7. The method of claim 6 , further including:
electrically connecting the gate contact to an input line;
electrically connecting the drain contact to an output line;
electrically connecting the n-type region of the n-type field-effect transistor to a relatively low voltage power supply, and
electrically connecting the p-type region of the p-type field-effect transistor to a relatively high voltage power supply.

8. The method of claim 7 , wherein the low voltage power supply is ground.

9. The method of claim 2 , further including:
recessing the gate electrode to form a first gate electrode portion extending laterally over the p-type region and a second gate electrode portion extending laterally over the n-type region, one of the first and second gate electrode portions having a larger width than the other of the first and second gate electrode portions, wherein the second trench is formed directly above the wider of the first and second gate electrode portions.

10. The method of claim 1 , wherein obtaining the monolithic structure includes:
obtaining a first structure including a substrate layer, the p-type region, the n-type region, a first counter-doped region between the substrate layer and the p-type region, and a second counter-doped region between the substrate layer and the n-type region;
forming a first dummy fin on the p-type region and a second dummy fin parallel to the first dummy fin on the n-type region;
forming a dielectric layer on the first structure;
forming a mask layer on the dielectric layer and extending over the p-type region, the n-type region, and the first and second dummy fins;
patterning the mask layer;
recessing the dielectric layer selective to the dummy fins and the p-type and n-type regions to form a recess extending between the dummy fins and down to the p-type and n-type regions;
forming a trench extending from the recess and through adjoining portions of the p-type region and the n-type region, through adjoining portions of the first and second counter-doped regions, and into the substrate layer;
removing the mask layer;
filling the trench with a dielectric material to form an isolation region, and
removing the dummy fins and the dielectric layer.

11. The method of claim 10 , wherein each of the dummy fins has a width of at least ten nanometers and not more than twenty-five nanometers.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Cheng Kangguo
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L27/11273

  Electricity · mapped topic

• H01L29/7853

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic