Vertical transistor fabrication and devices

Patent metadata

Field	Value
Publication number	US-9941411-B2
Application number	US-201615207247-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Dec 18, 2015
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

First claim

What is claimed is:

1. A vertical field effect transistor, comprising:
a first recess in a substrate, wherein the first recess has a first bottom surface;
a first drain on the first bottom surface of the first recess, wherein the first drain has the same crystal orientation as the first bottom surface;
a second recess in the substrate, wherein the second recess has a second bottom surface;
a second drain on the second bottom surface of a second recess formed in the substrate, wherein the second drain has the same crystal orientation as the second bottom surface;
one or more fin channels on the first drain, wherein the one or more fin channels on the first drain have the same crystal orientation as the first bottom surface;
one or more fin channels on the second drain, wherein the one or more fin channels on the second drain have the same crystal orientation as the second bottom surface;
a gate structure on each of the fin channels; and
sources on each of the fin channels associated with the first drain and the second drain, wherein the sources have the same crystal orientation as the fin channels.

2. The vertical field effect transistor of claim 1 further comprising a shallow trench isolation region in the substrate, wherein the shallow trench isolation region is between the first drain and the second drain, and a first low-k dielectric spacer in each of the troughs between the fin channels.

3. The vertical field effect transistor of claim 1 further comprising a first drain contact in electrical contact with the first drain, a first gate contact in electrical contact with the first gate, and a first source contact in electrical contact with each of the source(s) on the fin channels associated with the first drain.

4. The vertical field effect transistor of claim 1 , wherein from 1 to 25 fin channels are on and in electrical contact with the first drain, and from 1 to 25 fin channels are on and in electrical contact with the second drain.

5. The vertical field effect transistor of claim 1 , wherein the fin channels have a height in the range of about 30 nm to about 400 nm.

6. The vertical field effect transistor of claim 1 , wherein the first drain and the sources on the fin channels associated with the first drain comprise an n-doped material, and the second drain and the sources on the fin channels associated with the second drain comprise a p-doped material.

7. The vertical field effect transistor of claim 1 , wherein the first drain and the sources on the fin channels associated with the first drain comprise boron-doped silicon germanium (SiGe-B), and the second drain and the sources on the fin channels associated with the second drain comprise phosphorus-doped silicon carbide (SiC-P), and wherein the fin channels comprise intrinsic silicon.

8. The vertical field effect transistor of claim 1 , wherein the gate structure on each of the fin channels comprises a work function metal (WFM) cap.

9. A vertical field effect transistor, comprising:
a first recess in a substrate, wherein the first recess has a first bottom surface;
a first drain on the first bottom surface of the first recess, wherein the first drain has the same crystal orientation as the first bottom surface;
a second recess in the substrate, wherein the second recess has a second bottom surface;
a second drain on the second bottom surface of a second recess formed in the substrate, wherein the second drain has the same crystal orientation as the second bottom surface;
a shallow trench isolation region in the substrate, wherein the shallow trench isolation region is between the first drain and the second drain;
one or more fin channels on the first drain, wherein the one or more fin channels on the first drain have the same crystal orientation as the first bottom surface;
one or more fin channels on the second drain, wherein the one or more fin channels on the second drain have the same crystal orientation as the second bottom surface;
a low-k dielectric spacer between each of the fin channels on the first drain and between each of the fin channels on the second drain;
a gate structure on each of the fin channels; and
sources on each of the fin channels associated with the first drain and the second drain, wherein the sources have the same crystal orientation as the fin channels.

10. The vertical field effect transistor of claim 9 , wherein the first drain and sources on each of the fin channels associated with the first drain are doped to form an n-finFET.

11. The vertical field effect transistor of claim 10 , wherein the second drain and sources on each of the fin channels associated with the second drain are doped to form a p-finFET.

12. The vertical field effect transistor of claim 11 , wherein the n-finFET on the first drain and the p-finFET on the second drain are coupled to form a complementary metal oxide semiconductor (CMOS) transistor.

13. The vertical field effect transistor of claim 11 , wherein the gate structure on each of the fin channels surrounds the fin channel.

14. A vertical field effect transistor, comprising:
a first drain on a first bottom surface of a first recess, wherein the first drain has an area in the range of about 100 nm 2 to about 100,000 nm 2 ;
a second drain on a second bottom surface of a second recess formed in the substrate, wherein the second drain has an area in the range of about 100 nm 2 to about 100,000 nm 2 ;
a plurality of fin channels on the first drain; and
a plurality of fin channels on the second drain, wherein the first drain is boron-doped silicon germanium (SiGe-B), and the second drain is phosphorus-doped silicon carbide (SiC-P), and the first drain has a thickness in the range of about 10 nm to about 250 nm, and the second drain has a thickness in the range of about 10 nm to about 250 nm.

15. The vertical field effect transistor of claim 14 , further comprising a gate structure including a work function metal layer on each of the plurality of fin channels on the first drain and each of the plurality of fin channels on the second drain.

16. The vertical field effect transistor of claim 15 , wherein the work function metal layer includes at least one high-k oxide layer and at least one gate metal layer.

17. The vertical field effect transistor of claim 14 , wherein the first drain and the second drain have the same crystal orientation as the substrate.

18. The vertical field effect transistor of claim 14 , further comprising a shallow trench isolation region between the first drain and the second drain, wherein the shallow trench isolation region provides electrical isolation between the first drain and the second drain.

Assignees

• IBM

Inventors

• Anderson Brent A
• Doris Bruce B
• Kim Seong-Dong
• Venigalla Rajasekhar

Classifications

• H01L29/4966

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L27/11273

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic