Closely packed vertical transistors with reduced contact resistance

Patent metadata

Field	Value
Publication number	US-10096695-B2
Application number	US-201715618611-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Aug 26, 2016
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a semiconductor structure on a bottom doped region on a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin;
forming a top spacer on the gate;
forming a liner on the top spacer, the gate, and the semiconductor fin;
forming a dielectric layer on the liner;
removing portions of the liner to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer;
recessing a portion of the semiconductor fin such that a surface of the recessed semiconductor fin is flush to a surface of the top spacer;
forming a recessed opening by recessing portions of the liner from the exposed sidewall of the dielectric layer; and
forming a top epitaxy region on the exposed top surface of the semiconductor fin and the exposed sidewall of the dielectric layer, an extension of the top epitaxy region filling the recessed opening, said top epitaxy region confined between portions of the liner.

2. The method of claim 1 , further comprising further recessing the surface of the recessed semiconductor fin below the surface of the top spacer prior to forming the top epitaxy region.

3. The method of claim 1 , wherein the bottom spacer comprises a low-k dielectric and the top spacer comprises a low-k dielectric.

4. The method of claim 1 , wherein the liner has a thickness of about 3 nm to about 20 nm.

5. The method of claim 1 , wherein the liner has a thickness of about 3 nm to about 8 nm.

6. The method of claim 1 , wherein the liner comprises a nitride liner having a thickness of about 5 nm.

Assignees

• IBM

Inventors

• Bi Zhenxing
• Cheng Kangguo
• Li Juntao
• Xu Peng

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title