Stacked metal layers with different thicknesses

Patent metadata

Field	Value
Publication number	US-9620510-B2
Application number	US-201514969730-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Dec 19, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A semiconductor chip includes a plurality of stacked conductive layers. The plurality of stacked conductive layers includes a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is disposed on a first side of the second conductive layer. The third conductive layer is disposed on a second side of the second conductive layer. The third conductive layer is disposed on a side of the second conductive layer. The second conductive layer has a thickness which is thicker than those of the first conductive layer and the third conductive layer.

First claim

What is claimed is:

1. A semiconductor chip, comprising:
a plurality of first conductive lines formed in a first conductive layer, and extending along a first direction;
a plurality of second conductive lines formed in a second conductive layer, extending along a second direction substantially orthogonal to the first direction and crossing over the plurality of first conductive lines;
an array of cell locations located corresponding to where the plurality of first conductive lines cross over the plurality of second conductive lines; and
a plurality of third conductive lines formed in a third conductive layer and over the array of cell locations;
a plurality of switching devices each of which located in a corresponding one of the array of cell locations, and has a first terminal, a second terminal and a third terminal,
wherein
a first conductive path between the second terminal and the third terminal of the switching device is connected or disconnected in response to a signal at the first terminal;
a second conductive path does not exist between the first terminal the second terminal and between the first terminal and the third terminal;
a third conductive path among all first terminals of one row of the plurality of switching devices is formed using a corresponding second conductive line of the plurality of second conductive lines;
a fourth conductive path among all second terminals of one column of the plurality of switching devices is formed using a corresponding first conductive line of the plurality of first conductive lines;
the first conductive layer is disposed on a first side of the second conductive layer;
the third conductive layer is disposed on a second side of the second conductive layer; and
the second conductive layer has a thickness which is along a third direction substantially orthogonal to the first direction and the second direction, and is substantially thicker than those of the first conductive layer and the third conductive layer.

2. The semiconductor chip of claim 1 , further comprising:
a plurality of storage devices corresponding to the plurality of switching devices,
wherein
one storage device of the plurality of storage devices is configured with a storage node and a power supply node;
the storage node is charged or discharged through the power supply node; and
the storage node is coupled to the third terminal.

3. The semiconductor chip of claim 1 , wherein the thickness of the second conductive layer is thicker than that of the first conductive layer by a first factor equal to at least about 15% and that of the third conductive layer by a second factor equal to at least about 15%.

4. The semiconductor chip of claim 1 , wherein the thickness of the second conductive layer is thicker than that of the first conductive layer and/or the third conductive layer by a factor equal to at least about 30%.

5. The semiconductor chip of claim 1 , wherein
a fifth conductive path is not formed between each second conductive line of the plurality of second conductive lines and any fourth conductive line extending in parallel to the second conductive line and formed in a fourth conductive layer on the second side of the second conductive layer.

6. The semiconductor chip of claim 1 , further comprising:
a fourth conductive line extending in parallel and coupled to one of the plurality of second conductive lines, and formed in a fourth conductive layer on the second side of the second conductive layer.

7. The semiconductor chip of claim 6 , wherein
the fourth conductive layer has a thickness along the third direction which is at least substantially equal to that of the second conductive layer.

8. The semiconductor chip of claim 1 , wherein
a switching device of the plurality of switching devices comprises a FinFET;
the FinFET comprises:
a fin structure; and
a gate structure traversing the fin structure and wrapping around a portion of the fin structure;

the gate structure corresponds to the first terminal; and
portions of the fin structure on opposite sides of the gate structure correspond to the corresponding second terminal and third terminal.

9. The semiconductor chip of claim 1 , wherein
the third terminal of a switching device of the plurality of switching devices is coupled to a power supply node; and
the power supply node comprises one third conductive line of the plurality of third conductive lines.

10. An array cell, comprising:
a first conductive line;
a second conductive line;
a storage device configured with at least a storage node and a power supply node; and
a first access device coupling the first conductive line to the storage node in response to a signal at the second conductive line;
wherein
the first conductive line comprises a portion of a first metal line in a first conductive layer;
the second conductive line comprises a portion of a second metal line in a second conductive layer, wherein the first conductive layer is lower than the second conductive layer;
the power supply node comprises a portion of a third metal line in a third conductive layer and a portion of a fourth metal line in a fourth conductive layer, wherein the third conductive layer is upper than the second conductive layer and the fourth conductive layer is upper than the third conductive layer;
the second conductive layer has a thickness which is thicker than that of the third conductive layer; and
the fourth conductive layer has a thickness which is thicker than or substantially equal to that of the second conductive layer.

11. The array cell of claim 10 , wherein the thickness of the second conductive layer is thicker than that of the first conductive layer by a first factor equal to at least about 15% and that of the third conductive layer by a second factor equal to at least about 15%.

12. The array cell of claim 10 , wherein
the second conductive line further comprises a portion of a fifth metal line in the fourth conductive layer or in a fifth conductive layer upper than the second conductive layer;
the fifth metal line is extending in parallel with and coupled to the second metal line; and
the fourth conductive layer or the fifth conductive layer comprising the portion of the fifth metal line has a thickness which is at least substantially equal to the thickness of the second conductive layer.

13. The array cell of claim 12 , wherein
the thickness of the fourth conductive layer or the fifth conductive layer comprising the portion of the fifth metal line is larger than that of the second conductive layer by a factor equal to at least about 10%.

14. The array cell of claim 10 , wherein
the storage device is further configured with a complementary storage node and a higher power supply node;
the power supply node is a lower power supply node;
the array cell further comprises:
a complementary first conductive line; and
a second access device coupling the complementary first conductive line to the complementary storage node in response to the signal at the second conductive line;

the complementary first conductive line comprises a portion of a fifth metal line in the first conductive layer;
the higher power supply node comprises a portion of a sixth metal line in the first conductive layer; and
the first metal line and the fifth metal line are formed in parallel to and on opposite sides of the sixth metal line.

15. The array cell of claim 14 , wherein
the lower power supply node further comprises a portion of a seventh metal line and a portion of an eighth metal line in the second conductive layer;
the seventh metal line and the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L29/7851

  Electricity · mapped topic

• H01L27/10826

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic