Memory chip and layout design for manufacturing same

Patent metadata

Field	Value
Publication number	US-9564211-B2
Application number	US-201414317146-A
Country	US
Kind code	B2
Filing date	Jun 27, 2014
Priority date	Jun 27, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A static random access memory (SRAM) chip including a plurality of SRAM cells and a plurality of cell current tracking cells. Each of the SRAM cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices. Each cell current tracking cell include a first half-cell and a second half-cell. The first half-cell is different from the second half-cell.

First claim

What is claimed is:

1. A static random access memory (SRAM) chip comprising:
a plurality of SRAM cells, wherein each of the plurality of SRAM cells comprise:
a source voltage reference conductor;
a first ground reference conductor;
two cross-coupled inverters, and
two pass-gate devices; and

a plurality of cell current tracking cells, wherein each of the plurality of cell current tracking cells comprises:
a first half-cell, wherein the first half-cell comprises:
a first tracking bit-line conductor;
a first complementary metal oxide semiconductor (CMOS) comprising:
a first pull down (PD) device, and
a first pull up (PU) device, and

a first pass-gate device configured to track a current; and

a second half-cell, wherein the second half-cell comprises:
a second CMOS comprising:
a second PD device, and
a second PU device, and

a second pass-gate device configured to receive a word line signal;

a plurality of capacitance tracking cells, wherein each of the capacitance tracking cells of the plurality of capacitance tracking cells comprise:
a third half-cell comprising:
a third pass-gate device configured to track a bit-line capacitance, and
a third CMOS comprising:
a third PU device, and
a third PD device having a source node configured to be electrically floating;

wherein the first half-cell is different from the second half-cell;
wherein a gate of the first PD device of the first CMOS or a gate of the first PU device of the first CMOS is electrically connected to the source voltage reference conductor;
wherein a drain node of the second PU device is electrically isolated from a drain node of the second PD device;
wherein a gate node of the first pass-gate device is electrically connected to a tracking enable conductor; and
wherein a gate node of the second pass-gate device is electrically connected to a first word-line conductor.

2. The SRAM chip of claim 1 , wherein each of the capacitance tracking cells of the plurality of capacitance tracking cells further comprise:
a fourth half-cell, wherein the fourth half-cell comprises:
a fourth CMOS, and
a fourth pass-gate device configured as a dummy cell;

wherein the third half-cell is different from the fourth half-cell;
wherein the fourth CMOS comprises:
a fourth PU device, and
a fourth PD device, wherein a source node of the fourth PD device is electrically connected to a second ground reference conductor;

wherein a gate node of the third pass-gate device is electrically connected to the second ground reference conductor; and
wherein a gate node of the fourth pass-gate device is electrically connected to the first word-line conductor.

3. The SRAM chip of claim 2 , wherein the second ground reference conductor is electrically connected to the first ground reference conductor.

4. The SRAM chip of claim 2 , wherein the second ground reference conductor is electrically connected to a P_well conductor of a cell current tracking cell of the plurality of cell current tracking cells.

5. The SRAM chip of claim 1 , wherein a connection path from the gate of the first PD device of the first CMOS or a gate of the first PU device of the first CMOS to the source voltage reference conductor comprises:
a gate contact, and
a first via.

6. The SRAM chip of claim 2 , wherein a source node of the fourth PU device is electrically floating.

7. The SRAM chip of claim 1 , wherein a cell size of each of the plurality of SRAM cells and a cell size of each of the tracking cells of the plurality of cell current tracking cells or the plurality of capacitance tracking cells are substantially the same.

8. The SRAM chip of claim 1 , further comprising a memory cell array,
wherein the memory cell array is arranged by a plurality of columns and a plurality of rows;
wherein the plurality of SRAM cells and the tracking cells of the plurality of cell current tracking cells or the plurality of capacitance tracking cells are both located in the memory cell array; and
wherein the tracking cells of the plurality of cell current tracking cells or the plurality of capacitance tracking cells are located adjacent to an edge column of the plurality of SRAM cells.

9. The SRAM chip of claim 2 , wherein each of the plurality of cell current tracking cells and each of the plurality of capacitance tracking cells are located in a first column;
wherein the first column comprises at least 2 to 32 cell current tracking cells;
wherein a drain node of the first pass-gate device and a drain node of the third pass-gate device are each electrically connected to the first tracking bit-line conductor.

10. The SRAM chip of claim 9 , further comprising:
a plurality of edge cells, wherein the plurality of edge cells are arranged in a second column, and are adjacent to the first column;
wherein a portion of the plurality of edge cells comprise:
a first edge cell, and
a second edge cell, wherein the first edge cell comprises the tracking enable conductor which is electrically connected to a gate node of each of the plurality of cell current tracking cells in the first column.

11. A static random access memory (SRAM) chip comprises:
a plurality of SRAM cells;
a plurality of tracking cells;
a plurality of first edge cells;
a plurality of second edge cells, and
a plurality of well strap cells;
wherein each of the plurality of SRAM cells comprises:
a source voltage reference conductor;
a first ground reference conductor;
two cross-coupled inverters, and
two pass-gate devices;

wherein each of the plurality of tracking cells comprise:
a first half-cell, wherein the first half-cell comprises:
a first tracking bit-line conductor;
a first complementary metal oxide semiconductor (CMOS) comprising:
a first pull down (PD) device, and
a first pull up (PU) device, and

a first pass-gate device configured to track a current; and

a second half-cell, wherein the second half-cell comprises:
a second CMOS comprising:
a second PD device, and
a second PU device, and

a second pass-gate device;

wherein the first half-cell is different than the second half-cell;
wherein a gate node of the first pass-gate device is electrically connected to a tracking enable conductor;
wherein a gate node of the second pass-gate device is electrically connected to a first predetermined word-line conductor;

wherein each of the plurality of SRAM cells and each of the plurality of tracking cells are located in a memory cell array;
wherein the plurality of SRAM cells are arranged by a plurality of columns and a plurality of rows;
wherein each of the plurality of tracking cells are arranged in a first column;
wherein the first column is adjacent to an edge column of the plurality of SRAM cells;
a plurality of first edge cells, wherein the plurality of first edge cells are arranged in a second column, and are adjacent to the first column;
a plurality of second edge cells, wherein the plurality of second edge cells are arranged in a third column, and are adjacent to the plurality of columns of the plurality of SRAM cells;
wherein the plurality of first edge cells comprise the tracking enable conductor; and
wherein a cell size of each of the plurality of SRAM cells and a cell size of each of the plurality of tracking cells are substantially the same.

12. The SRAM chip of claim 11 , wherein the plurality of well strap cells are arranged in a first row and a second row, wherein the first row and the second row are located at opposing ends of the plurality of SRAM cells;
wherein each well strap cell of the plurality of well strap cells comprises:
a P-well strap conductor line, and
an N-Well strap con

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title