Static random access memory layout structure

Patent metadata

Field	Value
Publication number	US-9627036-B2
Application number	US-201514822911-A
Country	US
Kind code	B2
Filing date	Aug 11, 2015
Priority date	Jul 15, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

First claim

What is claimed is:

1. A static random access memory layout structure, comprising:
a semiconductor substrate, comprising:
a first active region extending along a first direction;
a second active region extending along the first direction;
a third active region extending along the first direction; and
a fourth active region extending along the first direction, wherein the first active region, the second active region, the third active region and the fourth active region sequentially arranged along a second direction;

a first gate line crossing the first active region and the second active region and extending to cover an end of the third active region;
a second gate line crossing the third active region and the fourth active region and extending to cover an end of the second active region, wherein the first gate line and the second gate line extend along the second direction respectively and are parallel to each other;
a first slot contact plug disposed between the first gate line and the second gate line and crossing the first active region and the second active region;
a second slot contact plug disposed between the first gate line and the second gate line and crossing the third active region and the fourth active region, wherein the first slot contact plug and the second slot contact plug are arranged along the second direction and disposed between the first gate line and the second gate line;
a first metal-zero interconnect disposed on the first slot contact plug and the second gate line and electrically connecting the first slot contact plug to the second gate line, wherein the first slot contact plug and the first metal-zero interconnect cross each other;
a second metal-zero interconnect disposed on the second slot contact plug and the first gate line and electrically connecting the second slot contact plug to the first gate line, wherein the second slot contact plug and the second metal-zero interconnect cross each other; and
a fifth gate line and a fifth metal-zero interconnect, wherein the fifth gate line is symmetric to the first gate line with respect to the second direction, and the fifth metal-zero interconnect is symmetric to the second metal-zero interconnect with respect to the second direction, and wherein the second metal-zero interconnect and the fifth metal-zero interconnect have a fourth gap therebetween, the first gate line and the fifth gate line have a fifth gap therebetween, and the fourth gap is smaller than the fifth gap.

2. The static random access memory layout structure according to claim 1 , wherein the first metal-zero interconnect covers an end of the second gate line, and the second metal-zero interconnect covers an end of the first gate line.

3. The static random access memory layout structure according to claim 1 , wherein the first slot contact plug covers an end of the first metal-zero interconnect, and the second slot contact plug covers an end of the second metal-zero interconnect.

4. The static random access memory layout structure according to claim 1 , further comprising:
a third gate line crossing the first active region, wherein the first slot contact plug is disposed between the first gate line and the third gate line; and
a third metal-zero interconnect disposed on the third gate line and crossing the third gate line.

5. The static random access memory layout structure according to claim 1 , further comprising:
a fourth gate line crossing the fourth active region, wherein the second slot contact plug is disposed between the second gate line and the fourth gate line; and
a fourth metal-zero interconnect disposed on the fourth gate line and crossing the fourth gate line.

6. The static random access memory layout structure according to claim 1 , further comprising a sixth gate line and a sixth metal-zero interconnect, wherein the sixth gate line is symmetric to the second gate line with respect to the second direction, and the sixth metal-zero interconnect is symmetric to the first metal-zero interconnect with respect to the second direction, wherein the first metal-zero interconnect and the sixth metal-zero interconnect have a sixth gap therebetween, the second gate line and the sixth gate line have a seventh gap therebetween, and the sixth gap is smaller than the seventh gap.

7. The static random access memory layout structure according to claim 1 , further comprising:
a third slot contact plug disposed on the first active region, wherein the first gate line is disposed between the first slot contact plug and the third slot contact plug, and the third slot contact plug is electrically connected to a low power line; and
a fourth slot contact plug disposed on the second active region, wherein the first gate line is disposed between the first slot contact plug and the fourth slot contact plug, and the fourth slot contact plug is electrically connected to a high power line.

8. The static random access memory layout structure according to claim 1 , further comprising:
a fifth slot contact plug disposed on the fourth active region, wherein the second gate line is disposed between the second slot contact plug and the fifth slot contact plug, and the fifth slot contact plug is electrically connected to a low power line; and
a sixth slot contact plug disposed on the third active region, wherein the second gate line is disposed between the second slot contact plug and the sixth slot contact plug, and the sixth slot contact plug is electrically connected to a high power line.

9. The static random access memory layout structure according to claim 1 , wherein the first slot contact plug and the second slot contact plug have a first gap therebetween, the second active region and the third active region have a second gap therebetween, the first gap is smaller than the second gap, the first metal-zero interconnect and the second metal-zero interconnect have a third gap therebetween, and the first gap is smaller than the third gap.

10. A static random access memory layout structure, comprising:
a semiconductor substrate, comprising:
a first active region extending along a first direction;
a second active region extending along the first direction;
a third active region extending along the first direction; and
a fourth active region extending along the first direction, wherein the first active region, the second active region, the third active region and the fourth active region sequentially arranged along a second direction;

a first gate line crossing the first active region and the second active region and extending to cover an end of the third active region;
a second gate line crossing the third active region and the fourth active region and extending to cover an end of the second active region, wherein the first gate line and the second gate line extend along the second direction respectively and are parallel to each other;
a first slot contact plug disposed between the first gate line and the second gate line and crossing the first active region and the second active region;
a second slot contact plug disposed between the first gate line and the second gate line and crossing the third active region and the fourth active region, wherein the first slot contact plug and the second slot contact plug are arranged along the second direction and disposed between the first gate line and the second gate line, wherein the first slot contact plug and the second slot contact plug have a first gap therebetween and the second active region and the third active region have a second gap therebetween, and the first gap is smaller than the second gap;
a first metal-zero interconnect disposed on the first slot contact plug and the second gate line and electrically connecti

Assignees

• United Microelectronics Corp

Inventors

• Yin Tan-Ya
• Chen Ming-Jui
• Huang Chia-Wei
• Tung Yu-Cheng
• Yang Chin-Sheng

Classifications

• G11C11/412 Primary

  using field-effect transistors only · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/0207

  Electricity · mapped topic