GOA driving circuit

Patent metadata

Field	Value
Publication number	US-9933889-B2
Application number	US-201615026595-A
Country	US
Kind code	B2
Filing date	Feb 25, 2016
Priority date	Jan 4, 2016
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Disclosed is a GOA driving circuit. In screen awakening stage, the first global control signal (Gas 1 ) controls the twelfth thin film transistor (T 12 ) to be activated for realizing the All Gate On function, and meanwhile controls the eleventh thin film transistor (T 11 ) to be activated to pull down the voltage level of the second node (P(n)); in reset stage, the reset signal (Reset) controls the first thin film transistor (T 1 ) to reset the voltage level of the second node (P(n)), and to set the duration of the single pulse of the reset signal (Reset) to be at least the sum of durations of initial pulses of the first, second clock signals; in touch scan stage, the second global control signal (Gas 2 ) controls the thirteenth thin film transistor (T 13 ) to be activated to make the output ends of the GOA units of the respective stages output composite signals (CS).

First claim

What is claimed is:

1. A GOA driving circuit, comprising GOA units of a plurality of stages which are cascade coupled, and the GOA unit of each stage comprises: a forward-backward scan control module, a basic output module, a basic output pull-down module, a first node control module, a second node control module, an output control module, a reset module, a voltage stabilizing module and a second node charging module;
n is set to be a positive integer, and except the GOA unit of the first stage, the GOA unit of the second stage, the GOA unit of the next to last stage and the GOA unit of the last stage, in the GOA unit of the nth stage:
the forward-backward scan control module comprises: a ninth thin film transistor, and a gate of the ninth thin film transistor is coupled to an output end of the two former n−2th stage GOA unit, and a source receives a forward scan control signal, and a drain is electrically coupled to a first node; and a tenth thin film transistor, and a gate of the tenth thin film transistor is coupled to an output end of the two latter stage n+2th GOA unit, and a source receives a backward scan control signal, and a drain is electrically coupled to the first node;
the basic output module comprises: a seventh thin film transistor, and a gate of the seventh thin film transistor is electrically coupled to a drain of a sixth thin film transistor, and a source receives a Mth clock signal, and a drain is electrically coupled to an output end; and a first capacitor, and one end of the first capacitor is electrically coupled to the drain of the sixth thin film transistor, and the other end is electrically coupled to the output end;
the basic output pull-down module comprises: an eighth thin film transistor, and a gate of the eighth thin film transistor is electrically coupled to a second node, and a source receives a composite signal, and a drain is electrically coupled to the output end; and a second capacitor, and one end of the second capacitor is electrically coupled to the second node, and the other end receives the composite signal;
the first node control module comprises: a fourth thin film transistor, and a gate of the fourth thin film transistor receives the Mth clock signal, and a source is electrically coupled to the a drain of a fifth thin film transistor, and a drain is electrically coupled to the first node; and the fifth thin film transistor, and a gate of the fifth thin film transistor is electrically coupled to the second node, and a source receives the composite signal;
the second node control module comprises: an eleventh thin film transistor, and a gate of the eleventh thin film transistor receives a first global control signal, and a source receives the composite signal, and a drain is electrically coupled to the second node;
the output control module comprises: a twelfth thin film transistor, and both a gate and a source of the twelfth thin film transistor receive the first global control signal, and a drain is electrically coupled to the output end; and a thirteenth thin film transistor, and a gate of the thirteenth thin film transistor receives a second global control signal, and a source receives the composite signal, and a drain is electrically coupled to the output end;
the reset module comprises: a first thin film transistor, and both a gate and a source of the first thin film transistor receives a reset signal, and a drain is electrically coupled to the second node;
the voltage stabilizing module comprises: the sixth thin film transistor, and a gate of the sixth thin film transistor receives a control voltage level, and a source is electrically coupled to the first node, and a drain is electrically coupled to the gate of the seventh thin film transistor;
the second node charging module comprises: a third thin film transistor, and a gate of the third thin film transistor receives a M−2th clock signal, and a source receives the control voltage level, and a drain is electrically coupled to the second node; and a second thin film transistor, and a gate of the second thin film transistor is electrically coupled to the first node, and a source receives the M−2th clock signal, and a drain is electrically coupled to the second node;
a working procedure of the GOA driving circuit comprises: a screen awakening stage, a reset stage, a normal display stage and a touch scan stage in order;
in the screen awakening stage, the first global control signal controls the twelfth thin film transistors and the eleventh thin film transistors of the GOA units of all stages to be activated, and the second global control signal controls the thirteenth thin film transistors of the GOA units of all stages to be deactivated; in the reset stage and the normal display stage, the first global control signal controls the twelfth thin film transistors and the eleventh thin film transistors of the GOA units of all stages to be deactivated, and the second global control signal controls the thirteenth thin film transistors of the GOA units of all stages to be deactivated; in the touch scan stage, the second global control signal controls the thirteenth thin film transistors of the GOA units of all stages to be activated, and the first global control signal controls the twelfth thin film transistors and the eleventh thin film transistors of the GOA units of all stages to be deactivated;
in the reset stage, the reset signal provides a single pulse to control the first thin film transistor to be activated to reset a voltage level of the second node, and a duration of the single pulse of the reset signal is at least a sum of durations of initial pulses of a first clock signal and a second clock signal;
in the reset stage and the normal display stage, voltage levels of the composite signal and the control voltage level are one high and one low, and voltage levels of the forward scan control signal and the backward scan control signal are one high and one low; in the touch scan stage, the composite signal is a pulse signal having the same frequency with a touch scan signal.

2. The GOA driving circuit according to claim 1 , wherein in the reset stage and the normal display stage, respective clock signals are all periodic pulse signals; in the touch scan stage, voltage levels of the respective clock signals are constant.

3. The GOA driving circuit according to claim 1 , wherein in the reset stage and the normal display stage, respective clock signals are all periodic pulse signals; in the touch scan stage, the respective clock signals are pulse signals having the same frequency with the touch scan signal.

4. The GOA driving circuit according to claim 2 , wherein the respective thin film transistors are all N-type thin film transistors;
in the screen awakening stage, the first global control signal is high voltage level, and the second global control signal is low voltage level; in the reset stage and the normal display stage, both the first global control signal and the second global control signal are low voltage levels; in the touch scan stage, the second global control signal is high voltage level, and the first global control signal is low voltage level;
in the reset stage and the normal display stage, a voltage level of the composite signal is low voltage level, and the control voltage level is high voltage level; all the respective clock signals are periodic high voltage level pulse signals.

5. The GOA driving circuit according to claim 3 , wherein the respective thin film transistors are all N-type thin film transistors;
in the screen awakening stage, the first global control signal is high voltage level, and the second global control signal is low voltage level; in the reset stage and the normal display stage, both the first global control signal and the second global control signal are low voltage levels; in the to

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Xiao Juncheng
• Yan Yao
• Cao Shangcao
• Dai Ronglei

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3659

  the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes · CPC title

• G09G2310/063

  Waveforms for resetting the whole screen at once · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title