Goa circuit, driving method thereof and liduid crystal display device

Patent metadata

Field	Value
Publication number	US-2017193944-A1
Application number	US-201514900684-A
Country	US
Kind code	A1
Filing date	Oct 21, 2015
Priority date	Sep 23, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

The disclosure provides a GOA circuit, a driving method thereof and a liquid crystal display device. The GOA circuit comprises a plurality of GOA units connected in cascade, wherein the N-stage GOA unit comprises a N-stage stage circuit, a N-stage Q point control circuit, a N-stage P point circuit, a N-stage output circuit and a switch circuit. The switch circuit is connected to the N-stage scan line for sending a turn-on signal to the N-stage scan line before the liquid crystal display device displays an image such that the thin-film transistor in the pixel connected to the N-stage scan line turns on. The disclosure may turn on the gate of each pixel when the display device is waken from the black screen to prevent the electricity leakage when the display device is wakened from the black screen, and may also increase the stability of the circuit.

First claim

What is claimed is:

1 . A GOA circuit, adapted for the liquid crystal display device, comprising:
a plurality of GOA units connected in cascade, N being an positive integer, wherein the N-stage GOA unit comprises a N-stage stage circuit, a N-stage Q point control circuit, a N-stage P point circuit, a N-stage output circuit and a switch circuit; wherein the N-stage stage circuit, the N-stage Q point control circuit, the N-stage P point control circuit, and the N-stage output circuit are connect to the Q point; the N-stage Q point control circuit, the N-stage P point control circuit and the N-stage output circuit are connected to the P point; the N-stage output circuit is further connected to the N-stage scan line; wherein the switch circuit is connected to the N-stage scan line, for sending a turn-on signal to the N-stage scan line before the liquid crystal display device displays an image such that the thin-film transistor in the pixel connected to the N-stage scan line turns on.

2 . The GOA circuit according to claim 1 , wherein the switch circuit comprises a first thin film transistor, having a source connected to the N-stage scan line and a drain connected to a gate and input with a turn-on signal; before the liquid crystal display device displays the image, the turn-on signal is a low voltage level signal such that the low voltage level signal is input to the N-stage scan line, thereby turning on the thin film transistor in the pixel connected to the N-stage scan line.

3 . The GOA circuit according to claim 1 , wherein the N-stage stage circuit comprises a second thin film transistor, a third thin film transistor and a forth thin film transistor;
wherein the gate of the second thin film transistor is input with the output signal of the (N−2)-stage GOA unit, and the drain is input with a forward scan signal; wherein the gate of the third thin film transistor is input with the output signal of the (N+2)-stage GOA unit, and the drain is input with a backward scan signal; wherein the gate of the forth thin film transistor is input with a first clock signal, the drain is connected to the source of the second thin film transistor and the third thin film transistor, and the source is connected to the Q point.

4 . The GOA circuit according to claim 1 , wherein the N-stage P point control circuit comprises a fifth thin film transistor and a sixth thin film transistor;
wherein the gate of the fifth thin film transistor is connected to the Q point, the drain is connected to a first clock signal, and the source is connected to the P point; wherein the gate of the sixth thin film transistor is input with the first clock signal, the drain is input with a low voltage level signal, and the source is connected to the P point.

5 . The GOA circuit according to claim 1 , wherein the N-stage Q point control circuit comprises a seventh thin film transistor and a eighth thin film transistor;
wherein the gate of the seventh thin film transistor is input with the second clock signal, the drain is connected to the Q-point; wherein the gate of the eighth thin film transistor is connected to the P point, the drain is connected to the source of the seventh thin film transistor, and the source is input with a high voltage level signal.

6 . The GOA circuit according to claim 1 , wherein the N-stage output circuit comprises a ninth thin film transistor and a tenth thin film transistor;
wherein the gate of the ninth thin film transistor is connected to the Q point, the drain is input with a second clock signal, and the source is connected to the N-stage scan line; wherein the gate of the tenth thin film transistor is connected to the P point, the drain is connected to the N-stage scan line, and the source is input with a high voltage level signal.

7 . The GOA circuit according to claim 1 , wherein the N-stage scan driving circuit further comprises a P point pull-up circuit;
wherein the P point pull-up circuit comprises an eleventh thin film transistor, having a gate input with a turn-on signal, a drain connected to the P point and a source input with a high voltage level signal.

8 . The GOA circuit according to claim 1 , wherein the N-stage scan driving circuit further comprises a resent circuit;
wherein the reset circuit comprises a twelfth thin film transistor, having a gate and a source input with a reset signal, and a drain connected to the P point.

9 . A method for driving a GOA circuit, adopted for a GOA circuit comprising a plurality of GOA units connected in cascade, N being an positive integer, wherein the N-stage GOA unit comprises a switch circuit connected to the N-stage scan line, the method comprises:
turning on the switch circuit of the GOA unit of each stage; inputting a turn-on signal to the scan line of each stage such that the thin film transistor in the pixel connected to the scan line of each stage turns on; and turning off the switch circuit of the GOA unit of each stage; starting scan from the first-stage GOA unit or the last-stage GOA unit.

10 . A liquid crystal display device comprising:
a display panel and a backlight; wherein the display panel comprising a GOA circuit, the GOA circuit comprising a plurality of GOA units connected in cascade, N being an positive integer, wherein the N-stage GOA unit comprises a N-stage stage circuit, a N-stage Q point control circuit, a N-stage P point circuit, a N-stage output circuit and a switch circuit; wherein the N-stage stage circuit, the N-stage Q point control circuit, the N-stage P point control circuit, and the N-stage output circuit are connect to the Q point; the N-stage Q point control circuit, the N-stage P point control circuit and the N-stage output circuit are connected to the P point; the N-stage output circuit is further connected to the N-stage scan line; wherein the switch circuit is connected to the N-stage scan line, for sending a turn-on signal to the N-stage scan line before the liquid crystal display device displays an image such that the thin-film transistor in the pixel connected to the N-stage scan line turns on.

11 . The liquid crystal display device according to claim 10 , wherein the switch circuit comprises a first thin film transistor, having a source connected to the N-stage scan line and a drain connected to a gate and input with a turn-on signal; before the liquid crystal display device displays the image, the turn-on signal is a low voltage level signal such that the low voltage level signal is input to the N-stage scan line, thereby turning on the thin film transistor in the pixel connected to the N-stage scan line.

12 . The liquid crystal display device according to claim 10 , wherein the N-stage stage circuit comprises a second thin film transistor, a third thin film transistor and a forth thin film transistor;
wherein the gate of the second thin film transistor is input with the output signal of the (N−2)-stage GOA unit, and the drain is input with a forward scan signal; wherein the gate of the third thin film transistor is input with the output signal of the (N+2)-stage GOA unit, and the drain is input with a backward scan signal; wherein the gate of the forth thin film transistor is input with a first clock signal, the drain is connected to the source of the second thin film transistor and the third thin film transistor, and the source is connected to the Q point.

13 . The liquid crystal display device according to claim 10 , wherein the N-stage P point control circuit comprises a fifth thin film transistor and a sixth thin film transistor;
wherein the gate of the fifth thin film transistor is connected to the Q point, the drain is c

Assignees

• Shenzhen China Star Optoelectronicstechnology Co Ltd
• Wuhan China Star Optoelectronics Technology Co Ltd
• Shenzhen China Star Optoelect

Inventors

• Xiao Juncheng
• Dai Ronglei
• Cao Shangcao
• Yan Yao

Classifications

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G02F2203/64

  Normally black display, i.e. the off state being black · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title