A GOA Circuit and a liquid crystal display

Patent metadata

Field	Value
Publication number	US-2017193956-A1
Application number	US-201514891646-A
Country	US
Kind code	A1
Filing date	Oct 21, 2015
Priority date	Sep 29, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

The invention disclosure a GOA circuit and a liquid crystal display. The GOA circuit including an electrical potential pull-down controlling circuit and a plurality of GOA sub circuits in cascade connection, the electrical potential pull-down controlling circuit comprising a first voltage limited transistor, a second filter transistor and a third transistor. The first voltage limited transistor, and the second filter transistor a reconnected in series and between the output terminal of the initial scanning signal, STV signal and the control terminal of the third transistor, the control terminal of the first voltage limited transistor and the first terminal of the third transistor is connected to the first power terminal and the second terminal of the third transistor is connected to the GOA sub circuit. By this design, the damage from the large static electricity to the GOA sub circuit can be avoided.

First claim

What is claimed is:

1 . A GOA circuit for liquid crystal display, the GOA circuit comprising:
An electrical potential pull-down controlling circuit and a plurality of GOA sub circuits in cascade connection; the electrical potential pull-down controlling circuit having a first voltage limited transistor, a second filter transistor and a third transistor, wherein the first voltage limited transistor and the second filter transistor are connected in series and between the output terminal of the initial scanning signal that is the STV signal and the control terminal of the third transistor, the control terminal of the first voltage limited transistor and the first terminal of the third transistor is connected to the first power terminal and the second terminal of the third transistor is connected to the GOA sub circuit.

2 . The GOA circuit according to claim 1 , wherein the first terminal of the second filter transistor is separately connected to the control terminal and the output terminal of the STV signal, the second terminal of the second filter transistor is connected to the first terminal of the first voltage limited transistor, and the second terminal of the first voltage limited transistor is connected to the control terminal of the third transistor.

3 . The GOA circuit according to claim 2 , wherein the first voltage limited transistor, the second filter transistor and the third transistor are PMOS transistors, the first terminal of the first voltage limited transistor is source, the second terminal is drain; the first terminal of the second filter transistor is source, the second terminal is drain; and the first terminal of the third transistor is source and the second terminal is drain.

4 . The GOA circuit according to claim 2 , wherein the first voltage limited transistor, the second filter transistor and the third transistor are NTFT transistors, the first terminal of the first voltage limited transistor is drain, the second terminal is source; the first terminal of the second filter transistor is drain, the second terminal is source; and the first terminal of the third transistor is drain and the second terminal is source.

5 . The GOA circuit according to claim 3 , wherein the electrical potential pull-down controlling circuit further comprising a fourth transistor, the first terminal of the fourth transistor is connected to the second terminal of the third transistor, the control terminal of the fourth transistor is connected to the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the GOA sub circuit, wherein the type of the fourth transistor and the third transistor is the same.

6 . The GOA circuit according to claim 4 , wherein the electrical potential pull-down controlling circuit further comprising a fourth transistor, the first terminal of the fourth transistor is connected to the second terminal of the third transistor, the control terminal of the fourth transistor is connected to the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the GOA sub circuit, wherein the type of the fourth transistor and the third transistor is the same.

7 . The GOA circuit according to claim 3 , wherein the electrical potential pull-down controlling circuit further comprising a fourth transistor, the first terminal of the fourth transistor is connected to the first power terminal, the control terminal of the fourth transistor is connected to the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the first terminal of the third transistor, wherein the type of the fourth transistor and the third transistor is the same.

8 . The GOA circuit according to claim 4 , wherein the electrical potential pull-down controlling circuit further comprising a fourth transistor, the first terminal of the fourth transistor is connected to the first power terminal, the control terminal of the fourth transistor is connected to the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the first terminal of the third transistor, wherein the type of the fourth transistor and the third transistor is the same.

9 . The GOA circuit according to claim 1 , wherein the first terminal of the first voltage limited transistor is connected to the output terminal of the STV signal, the second terminal of the first voltage limited transistor is connected to the first terminal of the second filter transistor, the control terminal of the second filter transistor is connected to the first terminal of the second filter transistor, and the second terminal of the second filter transistor is connected to the control terminal of the third transistor.

10 . The GOA circuit according to claim 1 , wherein the second terminal of the third transistor of the electrical potential pull-down controlling circuit is connected to the third level GOA sub circuit to the last level GOA sub circuit separately.

11 . The GOA circuit according to claim 1 , wherein the GOA circuit comprising a plurality of the electrical potential pull-down controlling circuit, each second terminal of the third transistor of each of the electrical potential pull-down controlling circuit is connected to the third level GOA sub circuit to the last level GOA sub circuit separately.

12 . A liquid crystal display having an array substrate, a color filter substrate and a liquid crystal layer formed between the array substrate and the color filter, wherein the array substrate having a GOA circuit, the GOA circuit comprising:
an electrical potential pull-down controlling circuit and a plurality of GOA sub circuits in cascade connection; the electrical potential pull-down controlling circuit comprising a first voltage limited transistor, a second filter transistor and a third transistor, wherein the first voltage limited transistor and the second filter transistor are connected in series and between the output terminal of the initial scanning signal, STV signal and the control terminal of the third transistor, the control terminal of the first voltage limited transistor and the first terminal of the third transistor is connected to the first power terminal and the second terminal of the third transistor is connected to the GOA sub circuit.

13 . The liquid crystal display according to claim 12 , wherein the first terminal of the second filter transistor is separately connected to the control terminal and the output terminal of the STV signal, the second terminal of the second filter transistor is connected to the first terminal of the first voltage limited transistor, and the second terminal of the first voltage limited transistor is connected to the control terminal of the third transistor.

14 . The liquid crystal display according to claim 13 , wherein the first voltage limited transistor, the second filter transistor and the third transistor are PMOS transistors, the first terminal of the first voltage limited transistor is source, the second terminal is drain; the first terminal of the second filter transistor is source, the second terminal is drain; and the first terminal of the third transistor is source and the second terminal is drain.

15 . The liquid crystal display according to claim 13 , wherein the first voltage limited transistor, the second filter transistor and the third transistor are NTFT transistors, the first terminal of the first voltage limited transistor is drain, the second terminal is source; the first terminal of the second filter transistor is drain, the second terminal is sourc

Assignees

• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Xiao Juncheng
• Zhao Mang

Classifications

• G11C19/184 Primary

  with field-effect transistors, e.g. MOS-FET · CPC title

• G02F2202/22

  Antistatic materials or arrangements · CPC title

• G02F1/133514

  Colour filters · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G02F1/136204

  Arrangements to prevent high voltage or static electricity failures · CPC title