Liquid crystal display device and gate driving circuit

Patent metadata

Field	Value
Publication number	US-9805680-B2
Application number	US-201514785907-A
Country	US
Kind code	B2
Filing date	Sep 21, 2015
Priority date	Sep 14, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A liquid crystal display device and a gate driving circuit are disclosed. The gate driving circuit includes multiple-stage gate driving units and a control chip. Each stage gate driving unit includes a first pulling control unit, a first pulling unit, a second pulling control unit, a second pulling unit, a first reset unit, a second reset unit. The control chip is used for pulling a first clock signal and a first voltage reference signal to a first voltage level. Accordingly, the scanning lines driven by the gate driving circuit are all turned on in order to stably realize an All-Gate-On function.

First claim

What is claimed is:

1. A gate driving circuit, wherein, the gate driving circuit includes multiple-stage gate driving units and a control chip, wherein each stage gate driving unit comprises:
a first pulling control circuit for outputting a first pulling control signal at a first node;
a first pulling circuit coupled with the first node, receiving a first clock signal, pulling a voltage level of an output terminal of a gate driving signal to a first voltage level according to the first pulling control signal and first clock signal in order to output the gate driving signal;
a second pulling control circuit for outputting a second pulling control signal at a second node;
a second pulling circuit coupled with the first node and the second node, receiving a first voltage reference signal, and pulling a voltage level of the first node to a second voltage level of the first voltage reference signal according to the second pulling control signal, and the second pulling circuit pulls a voltage level of the gate driving signal to the second voltage level;
a first reset circuit coupled with the first node, receiving a reset signal and the first voltage reference signal, pulling the voltage level of the first node to the second voltage level according to the reset signal; and
a second reset circuit coupled with the second node, receiving the reset signal and a second voltage reference signal, pulling a voltage level of the second node to a third voltage level of the second voltage reference signal according to the reset signal;
wherein, control chip is used for pulling the first clock signal and the first voltage reference signal to the first voltage level such that scanning lines driven by the gate driving circuit are all turned on;
wherein, the first pulling control circuit includes a first thin-film transistor and a second thin-film transistor;
a first terminal of the first thin-film transistor receives a first signal, a second terminal of the first thin-film transistor receives a gate driving signal of a previous stage, and a third terminal of the first thin-film transistor is connected with the first node; and
a first terminal of the second thin-film transistor receives a second signal; a second terminal of the second thin-film transistor receives a gate driving signal of a next stage, and a third terminal of the second thin-film transistor is connected with the first node;
wherein, the first pulling circuit includes a third thin-film transistor and a first capacitor, a first terminal of the third thin-film transistor receives the first clock signal, a second terminal of the third thin-film transistor is connected with the first node, a third terminal of the third thin-film transistor is the output terminal of the gate driving signal, and the first capacitor is connected between the second terminal and the third terminal of the third thin-film transistor;
wherein, the first reset circuit includes a fourth thin-film transistor, a first terminal of the fourth thin-film transistor is connected with the first node, a second terminal of the fourth thin-film transistor receives the reset signal, and a third terminal of the thin-film transistor receives the first voltage reference signal;
wherein, the second reset circuit includes a fifth thin-film transistor, a first terminal of the fifth thin-film transistor receives the second voltage reference signal, a second terminal of the fifth thin-film transistor receives the reset signal, and a third terminal of the fifth thin-film transistor is connected with the second node;
wherein, the second pulling control circuit includes a sixth thin-film transistor and a seventh thin-film transistor, a first terminal of the sixth thin-film transistor receives the second clock signal, a second terminal of the sixth thin-film transistor is connected with the first terminal of the fourth thin-film transistor, a third terminal of the sixth thin-film transistor is connected with a third terminal of the seventh thin-film transistor and the second node, a first terminal of the seventh thin-film transistor receives the second voltage reference signal, a second terminal of the seventh thin-film transistor receives the second clock signal; and
the second pulling circuit includes an eighth thin-film transistor, a ninth thin-film transistor, a tenth thin-film transistor and a second capacitor, a first terminal of the eighth thin-film transistor is connected with the second terminal of the third thin-film transistor, a second terminal of the eighth thin-film transistor receives the first clock signal, a third terminal of the eighth thin-film transistor is connected with a first terminal of the ninth thin-film transistor, a second terminal of the ninth thin-film transistor is connected with the third terminal of the seventh thin-film transistor, a third terminal of the ninth thin-film transistor receives the first voltage reference signal, a first terminal of the tenth thin-film transistor is connected with the third terminal of the thin-film transistor, a second terminal of the tenth thin-film transistor is connected with the second terminal of the ninth thin-film transistor, a third terminal of the tenth thin-film transistor receives the first voltage reference signal, the second capacitor is connected between the second terminal and the third terminal of the tenth thin-film transistor.

2. The gate driving circuit according to claim 1 , wherein, the gate driving unit further includes an eleventh thin-film transistor, a first terminal of the eleventh thin-film transistor is connected with the first node, a second terminal of the eleventh thin-film transistor receives the second voltage reference signal, a third terminal of the eleventh thin-film transistor is connected with the third terminal of the second thin-film transistor, the third terminal of the first thin-film transistor and the first terminal of the fourth thin-film transistor.

3. The gate driving circuit according to claim 2 , wherein, the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fourth thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, the eighth thin-film transistor, the ninth thin-film transistor, and the tenth thin-film transistor are all P-type thin-film transistors; and
when the rest signal is at a low voltage level, the fourth thin-film transistor is turned on, the voltage level of the second terminal of the third thin-film transistor is pulled to the second voltage level, the second thin-film transistor is turned off; the fifth thin-film transistor is turned on, the voltage level of the second terminal of the tenth thin-film transistor is pulled to the third voltage level, the tenth thin-film transistor is turned on in order to pull the voltage level of the gate driving signal to the second voltage level.

4. The gate driving circuit according to claim 3 , wherein, each of the first voltage level and the third voltage level is a low level, and the second voltage level is a high level.

5. The gate driving circuit according to claim 2 , wherein, the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fourth thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, the eighth thin-film transistor, the ninth thin-film transistor, the tenth thin-film transistor, and the eleventh thin-film transistor are all N-type thin-film transistors.

6. A liquid crystal display device, wherein, the liquid crystal display device includes a gate driving circuit, the gate driving circuit includes multiple-stage gate driving units and a control chip, and each stage gate driving unit comprises:
a first pulling cont

Assignees

• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd
• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Xiao Juncheng
• Dai Ronglei
• Yan Yao
• Cao Shangcao

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0871

  with level shifting · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title