Method for producing integrated circuit memory cells with less dedicated lithographic steps

Patent metadata

Field	Value
Publication number	US-9929165-B1
Application number	US-201615278112-A
Country	US
Kind code	B1
Filing date	Sep 28, 2016
Priority date	Sep 28, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.

First claim

What is claimed is:

1. A method of producing an integrated circuit comprising:
patterning a source line photoresist mask to overlie a drain line area of a substrate while exposing a source line area of the substrate, wherein the source line area is defined between a first memory cell and a second memory cell, and wherein the drain line area is defined between the second memory cell and a third memory cell;
forming a source line in the source line area;
concurrently forming a source line dielectric and a drain line dielectric, wherein the source line dielectric overlies the source line and the drain line dielectric overlies the drain line area;
patterning a drain line photoresist mask to overlie the source line in an active section of the integrated circuit, wherein the drain line photoresist mask exposes the source line in a strap section of the integrated circuit, and wherein the drain line photoresist mask exposes the drain line area; and
removing the drain line dielectric from overlying the drain line area, wherein a thickness of the source line dielectric in the strap section is reduced while removing the drain line dielectric from overlying the drain line area.

2. The method of claim 1 wherein patterning the source line photoresist mask comprises patterning the source line photoresist mask wherein the first memory cell, the second memory cell, and the third memory cell each comprise a floating gate overlying the substrate, a control gate dielectric overlying the floating gate, and a control gate overlying the control gate dielectric.

3. The method of claim 2 wherein patterning the source line photoresist mask comprises patterning the source line photoresist mask wherein each of the first memory cell, the second memory cell, and the third memory cell directly overlie a shallow trench isolation structure.

4. The method of claim 3 wherein pattering the source line photoresist mask comprises patterning the source line photoresist mask wherein the first memory cell, the second memory cell, and the third memory cell comprise a floating gate dielectric overlying the substrate and directly underlying the floating gate, and wherein the floating gate dielectric is adjacent to the shallow trench isolation structure.

5. The method of claim 1 further comprising:
removing at least a portion of the source line dielectric overlying the strap section after reducing the thickness of the source line dielectric in the strap section.

6. The method of claim 1 wherein:
forming the source line dielectric overlying the source line while forming the drain line dielectric overlying the drain line area comprises forming the source line dielectric where the thickness of the source line dielectric is greater than a thickness of the drain line dielectric.

7. The method of claim 1 further comprising:
forming an interlayer dielectric overlying the source line and the drain line area; and
forming a contact in electrical communication with the source line in the strap section, wherein the contact is formed in the absence of a lithographic step dedicated to removing the source line dielectric from overlying the source line in the strap section.

8. The method of claim 7 further comprising:
forming a via through the interlayer dielectric, wherein the via directly overlies the source line in the strap section.

9. The method of claim 8 further comprising:
removing the source line dielectric from overlying the source line within the via.

10. The method of claim 8 further comprising:
forming a silicide overlying the source line within the via prior to forming the contact.

11. A method of producing an integrated circuit comprising:
patterning a source line photoresist mask to overlie a drain line area while exposing a source line area within an active section of the integrated circuit, wherein the source line photoresist mask overlies the source line area in a strap section of the integrated circuit, wherein the source line area is within a substrate between a first memory cell and a second memory cell, and wherein the drain line area is within the substrate between the second memory cell and a third memory cell;
forming a source line in the source line area of the active section; and
concurrently forming a source line dielectric and a drain line dielectric, wherein the source line dielectric overlies the source line area in both the active section and the strap section and the drain line dielectric overlies the drain line area in both the active section and the strap section;
forming an interlayer dielectric overlying the source line area and the drain line area;
forming a via through the interlayer dielectric to the source line area in the strap section;
removing the source line dielectric from overlying the source line area within the via; and
forming a contact in electrical communication with the source line area in the strap section.

12. The method of claim 11 further comprising:
forming the source line in the strap section by implanting conductivity determining impurities into the source line area exposed through the via prior to forming the contact.

13. The method of claim 11 wherein:
forming the source line dielectric overlying the source line area comprises forming the source line dielectric wherein a thickness of the source line dielectric is within about 10 percent of a thickness of the drain line dielectric.

14. The method of claim 11 wherein patterning the source line photoresist mask comprises:
patterning the source line photoresist mask wherein the first memory cell, the second memory cell and the third memory cell each comprise a floating gate overlying the substrate, a control gate dielectric overlying the floating gate, and a control gate overlying the control gate dielectric.

15. The method of claim 14 wherein patterning the source line photoresist mask comprises patterning the source line photoresist mask wherein the first memory cell, the second memory cell, and the third memory cell each directly overlie a shallow trench isolation structure.

16. The method of claim 15 wherein pattering the source line photoresist mask comprises patterning the source line photoresist mask wherein the first memory cell, the second memory cell, and the third memory cell each comprise a floating gate dielectric overlying the substrate and directly underlying the floating gate, and wherein the floating gate dielectric is adjacent to the shallow trench isolation structure.

17. The method of claim 15 wherein forming the contact in electrical communication with the source line area of the strap section comprises forming the contact in the absence of a lithographic step dedicated to removing the source line dielectric from overlying the source line area within the strap section.

18. A method of producing an integrated circuit comprising:
patterning a source line photoresist mask to overlie a drain line area while exposing a source line area within an active section of the integrated circuit, wherein the source line photoresist mask overlies the source line area in a strap section of the integrated circuit, wherein the source line area is defined within a substrate between a first memory cell and a second memory cell, wherein the drain line area is defined within the substrate between the second memory cell and a third memory cell;
forming a source line in the source line area within the active section of the integrated circuit;
concurrently forming a source line dielectric and a drain line dielectric, wherein the source line dielectric overlies the sourc

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Luo Laiqiang
• Kong Yu Jin Eugene
• Wang Daxiang
• Zhang Fan
• Shum Danny Pak-Chum
• Li Pinghui
• Teo Zhiqiang
• Tan Juan Boon
• Siah Soh Yun
• Leong Pey Kin

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/414

  of metal-silicide materials · CPC title