Connection arrangements for integrated lateral diffusion field effect transistors

Patent metadata

Field	Value
Publication number	US-9923059-B1
Application number	US-201715588357-A
Country	US
Kind code	B1
Filing date	May 5, 2017
Priority date	Feb 20, 2017
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

In an active layer over a semiconductor substrate, a semiconductor device has a first lateral diffusion field effect transistor (LDFET) that includes a source, a drain, and a gate, and a second LDFET that includes a source, a drain, and a gate. The source of the first LDFET and the drain of the second LDFET are electrically connected to a common node. A first front-side contact and a second front-side contact are formed over the active layer, and a substrate contact electrically connected to the semiconductor substrate is formed. Each of the first front-side contact, the second front-side contact, and the substrate contact is electrically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate supporting an overlying active layer;
a first lateral diffusion field effect transistor (LDFET) in the active layer and comprising a source, a drain, and a gate;
a second LDFET in the active layer and comprising a source, a drain, and a gate;
a common node electrically connected to the source of the first LDFET and the drain of the second LDFET;
a first front-side contact over the active layer and electrically connected to a first one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a second front-side contact over the active layer and electrically connected to a second one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a substrate contact electrically connected to the semiconductor substrate and a third one of: the drain of the first LDFET, the source of the second LDFET, and the common node; and
a semiconductor package comprising an electrically conductive paddle and perimeter package leads, wherein a first electrically conductive clip is electrically connected to the first front-side contact and a first set of one or more of the perimeter package leads, a second electrically conductive clip is electrically connected to the second front-side contact and a second set of one or more of the perimeter package leads, and the substrate contact is electrically connected to the paddle;
wherein each of the first front-side contact, the second front-side contact, and the substrate contact is electrically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.

2. The semiconductor device of claim 1 , further comprising a buried dielectric layer between the semiconductor substrate and the active layer; wherein the substrate contact extends through the buried dielectric layer.

3. The semiconductor device of claim 2 , further comprising, between the first and second LDFETs, a dielectric isolation barrier that extends through the active layer to the buried dielectric layer.

4. The semiconductor device of claim 2 , wherein the substrate contact extends through the active layer.

5. The semiconductor device of claim 4 , wherein the substrate contact extends through one of the sources and drains of the first and second LDFETs.

6. The semiconductor device of claim 4 , wherein the substrate contact extends through the active layer in a region free of any of the sources and drains of the first and second LDFETs, and the substrate contact is electrically connected to one of the sources and drains of the first and second LDFETs by an electrical connection that extends laterally over the active layer and downward through one of the sources and drains of the first and second LDFETs.

7. The semiconductor device of claim 6 , wherein the substrate contact extends through an opening in the active layer that extends from the buried dielectric layer through the active layer.

8. The semiconductor device of claim 7 , wherein the substrate contact and the opening in the active layer have respective widths in a lateral dimension orthogonal to an axial dimension along which the substrate contact extends, and the width of the opening in the active layer is greater than the width of the substrate contact.

9. The semiconductor device of claim 4 , wherein the substrate contact extends through the active layer to the substrate along an axial dimension, the substrate contact has a top portion that extends into the active layer and is characterized by a first width in a lateral dimension orthogonal to the axial dimension, and the substrate contact has a bottom portion that extends into the active layer and is characterized by a second width in the lateral dimension that is smaller than the first width.

10. The semiconductor device of claim 5 , wherein the substrate contact is electrically connected to the common node.

11. The semiconductor device of claim 5 , wherein the substrate contact is electrically connected to one of the first and second front-side contacts.

12. A semiconductor device, comprising:
a semiconductor substrate supporting an overlying active layer;
a first lateral diffusion field effect transistor (LDFET) in the active layer and comprising a source, a drain, and a gate;
a second LDFET in the active layer and comprising a source, a drain, and a gate;
a common node electrically connected to the source of the first LDFET and the drain of the second LDFET;
a first front-side contact over the active layer and electrically connected to a first one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a second front-side contact over the active layer and electrically connected to a second one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a substrate contact electrically connected to the semiconductor substrate and a third one of: the drain of the first LDFET, the source of the second LDFET, and the common node; and
a buried dielectric layer between the semiconductor substrate and the active layer;
wherein the substrate contact extends through the buried dielectric layer;
wherein the substrate contact extends through the active layer;
wherein each of the first front-side contact, the second front-side contact, and the substrate contact is electrically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node; and
wherein the substrate contact comprises a first set of parallel substrate sub-contacts that are interleaved with a second set of parallel channel sub-contacts that are connected to one of the sources and drains of the first and second LDFETs, wherein the respective sub-contacts of the first and second sets extend to a surface above the active layer where they are alternately arranged in a row.

13. A method of fabricating a semiconductor device, comprising:
in an active layer over a semiconductor substrate, forming a first lateral diffusion field effect transistor (LDFET) comprising a source, a drain, and a gate, and a second LDFET comprising a source, a drain, and a gate;
electrically connecting the source of the first LDFET and the drain of the second LDFET to a common node;
over the active layer, forming a first front-side contact and a second front-side contact;
forming a substrate contact electrically connected to the semiconductor substrate;
electrically connecting the first front-side contact to a first set of one or more perimeter package leads of a semiconductor package with a first electrically conductive clip;
electrically connecting the second front-side contact to a second set of one or more perimeter package leads of the semiconductor package with a second electrically conductive clip; and
electrically connecting the substrate contact to a paddle of the semiconductor package;
wherein each of the first front-side contact, the second front-side contact, and the substrate contact is electrically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.

14. The method of claim 13 , further comprising:
forming a buried dielectric layer between the semiconductor substrate and the active layer, wherein the substrate contact extends through the buried dielectric layer; and
forming between the first and second LDFETs a dielectric isolation barrier that extends through the active layer to the buried dielectric layer.

Assignees

• Silanna Asia Pte Ltd

Inventors

• Tu Shanghui Larry
• Stuber Michael A
• Tasbas Befruz
• Molin Stuart B
• Jiang Raymond

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/761

  of strap connectors · CPC title