Semiconductor devices and structures

Patent metadata

Field	Value
Publication number	US-9202760-B2
Application number	US-201213533379-A
Country	US
Kind code	B2
Filing date	Jun 26, 2012
Priority date	Jun 26, 2012
Publication date	Dec 1, 2015
Grant date	Dec 1, 2015

Abstract

Devices, semiconductor structures and methods are provided, where a substrate is around a semiconductor device is biased via a resistive element.

First claim

In the claims:

1. A semiconductor structure, comprising:
a first well of a first polarity provided in a substrate of a second polarity different from said first polarity,
a well contact provided in said first well of the first polarity to be coupled with a first supply voltage,
a semiconductor device in said first well,

a second well of said second polarity with a higher doping concentration than said substrate arranged around said first well of the first polarity, said second well of the second polarity being coupled to a resistive element that is distinct from the substrate, said resistive element to be coupled with a second supply voltage and is located above the substrate, wherein said resistive element comprises at least one of a resistor or a transistor.

2. A semiconductor structure, comprising:
a first well of a first polarity provided in a substrate of a second polarity different from said first polarity,
a well contact provided in said first well of the first polarity to be coupled with a first supply voltage,
a semiconductor device in said first well,

a second well of said second polarity with a higher doping concentration than said substrate arranged around said first well of the first polarity, said second well of the second polarity being coupled to a resistive element that is distinct from the substrate, said resistive element to be coupled with a second supply voltage and is located above the substrate;
a third well of said second polarity arranged in said first well of said first polarity and a fourth well of said second polarity arranged in said first well of the first polarity, and a gate electrode on said substrate between said third well and said fourth well;
a fifth well of said second polarity having a higher doping concentration than said substrate and being arranged in said substrate,
a distance between said fifth well of said second polarity and said second well of said second polarity being at least a predetermined distance, the fifth well of said second polarity to be coupled with said second supply voltage via a connection having a resistance smaller than the resistance of said resistive element.

3. The semiconductor structure of claim 2 , further comprising
a sixth well of said first polarity being provided between said second well of said second polarity and said fifth well of said second polarity, said sixth well of said first polarity to be coupled with a third supply voltage.

Assignees

• Domanski Krzysztof
• Infineon Technologies Ag

Inventors

• Domanski Krzysztof

Classifications

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W44/401

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title