Wafer-scale testing of photonic integrated circuits using horizontal spot-size converters

US9922887B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9922887-B2
Application numberUS-201314103659-A
CountryUS
Kind codeB2
Filing dateDec 11, 2013
Priority dateDec 11, 2012
Publication dateMar 20, 2018
Grant dateMar 20, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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Disclosed herein are methods, structures, and devices for wafer scale testing of photonic integrated circuits.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method, comprising: obtaining a wafer comprising a plurality of photonic integrated circuits wherein a first photonic integrated circuit of the plurality of photonic integrated circuits comprises a test circuit and a second photonic integrated circuit of the plurality of photonic integrated circuits comprises a horizontal spot-size converter; coupling light to the test circuit using a grating coupler disposed on a surface of the first photonic integrated circuit, wherein the light is out-of-plane with respect to the surface; and operating the test circuit to test the second photonic integrated circuit via the horizontal spot-size converter. 2. The method according to claim 1 , further comprising obtaining a plurality of chips by dicing a portion of the plurality of photonic integrated circuits off the wafer. 3. The method according to claim 1 , wherein the test circuit comprises a polarization splitter. 4. The method of claim 1 , wherein the horizontal spot-size converter is a first horizontal spot-size converter, and wherein operating the test circuit to test the second photonic integrated circuit via the horizontal spot-size converter comprises optically coupling a second horizontal spot-size converter disposed on the first photonic integrated circuit to the first horizontal spot-size converter. 5. The method of claim 1 , wherein operating the test circuit comprises splitting polarization of a test signal and providing the test signal over a trench. 6. The method of claim 1 , further comprising filling a region formed between the first photonic integrated circuit and the second photonic integrated circuit with a fluid. 7. The method of claim 1 , further comprising separating the light into two or more polarization components, and wherein operating the test circuit to test the second photonic integrated circuit comprises coupling at least one of the two or more polarization components between the test circuit and the horizontal spot-size converter. 8. The method according to claim 1 , wherein the first photonic integrated circuit is in a neighboring relationship to the second photonic integrated circuit. 9. The method according to claim 5 , wherein operating the test circuit to test the second photonic integrated circuit via the horizontal spot-size converter comprises optically coupling the test circuit to the horizontal spot-size converter through a trench. 10. The method according to claim 1 , wherein the second photonic integrated circuit further comprises an intermediate waveguide optically coupled to the horizontal spot-size converter, wherein the horizontal spot-size converter and the intermediate waveguide are made of different materials. 11. The method according to claim 10 , wherein the intermediate waveguide is cantilevered. 12. The method according to claim 11 , wherein the cantilevered intermediate waveguide is adjacent a region that is filled with a fluid. 13. An apparatus comprising: a wafer comprising a plurality of photonic integrated circuits; a first photonic integrated circuit of the plurality of photonic integrated circuits comprising a test circuit; a second photonic integrated circuit of the plurality of photonic integrated circuits comprising a horizontal spot-size converter, wherein the horizontal spot-size converter is an inverted taper; wherein the test circuit is configured to test the second photonic integrated circuit via the horizontal spot-size converter. 14. The apparatus according to claim 13 , wherein the second photonic integrated circuit comprises an intermediate waveguide optically coupled to the inverted taper; wherein the inverted taper and the intermediate waveguide are made of different materials. 15. The apparatus according to claim 13 , wherein the test circuit comprises a grating coupler. 16. The apparatus of claim 13 , wherein the test circuit comprises a polarization splitter. 17. The apparatus of claim 13 , wherein the horizontal spot-size converter is a first horizontal spot-size converter, and wherein the first photonic integrated circuit further comprises a second horizontal spot-size converter configured to optically couple the test circuit to the first horizontal spot-size converter. 18. The apparatus of claim 13 , wherein the wafer is at least partially made of silicon. 19. The apparatus according to claim 13 , wherein the test circuit is configured to optically couple to the horizontal spot-size converter through a trench. 20. The apparatus according to claim 19 , wherein the horizontal spot-size converter forms an angle with respect to a normal to the trench that is greater than zero.

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Classifications

  • Structural arrangements therefor · CPC title

  • H10P74/20Primary

    characterised by the properties tested or measured, e.g. structural or electrical properties · CPC title

  • in which light is projected perpendicularly to the axis of the fibre or waveguide for monitoring a section thereof · CPC title

  • high refractive index type, i.e. high-contrast waveguides · CPC title

  • utilising prism or grating {(G02B6/293 takes precedence)} · CPC title

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Frequently asked questions

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What does patent US9922887B2 cover?
Disclosed herein are methods, structures, and devices for wafer scale testing of photonic integrated circuits.
Who is the assignee on this patent?
Acacia Communications Inc
What technology area does this patent fall under?
Primary CPC classification H10P74/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 20 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).