Semiconductor Device

Patent metadata

Field	Value
Publication number	US-2016133541-A1
Application number	US-201514886312-A
Country	US
Kind code	A1
Filing date	Oct 19, 2015
Priority date	Nov 7, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate arranged on an upper surface of the semiconductor element with an adhesive arranged in between, and an encapsulation resin filling a gap between the heat dissipation plate and the wiring substrate. The heat dissipation plate includes a body and a projection. The body is overlapped with the semiconductor element in a plan view and has a larger planar shape than the semiconductor element. The projection is formed integrally with the body. The projection projects outward from an end of the body and is located below the body. The encapsulation resin covers upper and lower surfaces of the projection. The body includes an upper surface exposed from the encapsulation resin.

First claim

1 . A semiconductor device comprising:
a wiring substrate; a semiconductor element mounted on the wiring substrate; a heat dissipation plate arranged on an upper surface of the semiconductor element with an adhesive arranged in between; and an encapsulation resin that fills a gap between the heat dissipation plate and the wiring substrate; wherein the heat dissipation plate includes:
a body overlapped with the semiconductor element in a plan view, wherein the body has a larger planar shape than the semiconductor element; and
a projection formed integrally with the body, wherein the projection projects outward from an end of the body and is located below the body,
the encapsulation resin covers upper and lower surfaces of the projection, and the body includes an upper surface exposed from the encapsulation resin.

2 . The semiconductor device according to claim 1 , wherein the projection projects outward from one of a plurality of corners of the body or from a portion of one of a plurality of sides of the body.

3 . The semiconductor device according to claim 1 , wherein the projection includes:
a connection portion that extends downward from the end of the body; and an extension that extends outward from an end of the connection portion in parallel to the body.

4 . The semiconductor device according to claim 3 , wherein
the extension, the encapsulation resin, and the wiring substrate each include an outer side surface, and the outer side surface of the extension is flush with the outer side surface of the encapsulation resin and the outer side surface of the wiring substrate.

5 . The semiconductor device according to claim 3 , wherein
the extension includes a first end, which is connected to the connection portion, and a second end, which is located at a side opposite to the first end, and the second end of the extension includes a cutaway portion.

6 . The semiconductor device according to claim 1 , wherein the projection is electrically connected to a ground wiring, which is formed on an upper surface of the wiring substrate, by an electrically conductive adhesive.

Assignees

• Shinko Electric Ind Co

Inventors

• Ozawa Takashi
• Tokunaga Kazuki

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title