Vertical field effect transistor having U-shaped top spacer

Patent metadata

Field	Value
Publication number	US-9859166-B1
Application number	US-201715413588-A
Country	US
Kind code	B1
Filing date	Jan 24, 2017
Priority date	Jan 24, 2017
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer within troughs defined by the plurality of fins and depositing a high-k dielectric layer, a work function material layer, and a conducting layer. The method further includes etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins, depositing a liner dielectric, and etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration. The method further includes forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
forming a plurality of fins over a source/drain region;
forming a first spacer within troughs defined by the plurality of fins;
depositing a high-k dielectric layer, a work function material layer, and a conducting layer;
etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins;
depositing a liner dielectric;
etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration; and
forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.

2. The method of claim 1 , wherein each of the plurality of fins includes a hard mask deposited thereon.

3. The method of claim 1 , wherein the conducting layer is Tungsten (W).

4. The method of claim 1 , wherein the liner dielectric is a silicon nitride (SiN) liner.

5. The method of claim 1 , wherein an organic planarization layer (OPL) is deposited over the troughs of the plurality of fins.

6. The method of claim 5 , wherein the OPL layer is removed before the epitaxial layer is formed.

7. The method of claim 1 , wherein a nitride cap is deposited over the epitaxial layer.

8. The method of claim 1 , wherein the plurality of U-shaped spacers are formed between the plurality of fins.

9. The method of claim 1 , wherein the plurality of U-shaped spacers are formed over a section of the high-k dielectric layer, the work function material layer, and the conducting layer.

10. A method of forming a semiconductor structure, the method comprising:
forming a plurality of fins over a substrate;
forming a spacer adjacent a lower section of the plurality of fins;
depositing a liner dielectric; and
etching portions of the liner dielectric to form a plurality U-shaped spacers adjacent an upper section of the plurality of fins.

11. The method of claim 10 , further comprising forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of U-shaped spacers and the epitaxial layer.

12. The method of claim 11 , wherein a nitride cap is deposited over the epitaxial layer.

13. The method of claim 10 , further comprising depositing a high-k dielectric layer, a work function material layer, and a conducting layer over the plurality of fins before depositing the liner dielectric.

14. The method of claim 13 , further comprising etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins to receive the liner dielectric.

15. The method of claim 10 , wherein the liner dielectric is a silicon nitride (SiN) liner.

16. The method of claim 10 , wherein the plurality of U-shaped spacers are formed between the plurality of fins.

17. A semiconductor structure, comprising:
a plurality of fins formed over a source/drain region;
a first spacer formed within troughs defined by the plurality of fins;
a high-k dielectric layer, a work function material layer, and a conducting layer deposited over the plurality of fins, where the high-k dielectric layer, the work function material layer, and the conducting layer are etched to form recesses between the plurality of fins;
a liner dielectric etched to form a plurality of second spacers having a U-shaped configuration; and
an epitaxial layer formed over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.

18. The structure of claim 17 , wherein an organic planarization layer (OPL) is deposited over the troughs of the plurality of fins.

19. The structure of claim 17 , wherein the OPL layer is removed before the epitaxial layer is formed.

20. The structure of claim 18 , wherein a nitride cap is deposited over the epitaxial layer.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Miao Xin
• Xu Wenyu
• Zhang Chen

Classifications

• H01L29/1037

  Electricity · mapped topic

• H01L21/823487 Primary

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L21/823468

  Electricity · mapped topic