CMOS-based thermopile with reduced thermal conductance

Patent metadata

Field	Value
Publication number	US-9853086-B2
Application number	US-201615350694-A
Country	US
Kind code	B2
Filing date	Nov 14, 2016
Priority date	May 30, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

First claim

What is claimed is:

1. A method of forming an integrated circuit, the method comprising:
providing a substrate comprising silicon-based semiconductor material;
forming isolation trenches in the substrate, the substrate between the isolation trenches providing active areas of the integrated circuit, the active areas including active areas for an NMOS transistor and a PMOS transistor in an area for CMOS transistors of the integrated circuit, and for n-type thermoelectric elements and p-type thermoelectric elements of an embedded thermoelectric device of the integrated circuit;
subsequently implanting germanium into the n-type thermoelectric elements and the p-type thermoelectric elements with a dose sufficient to provide at least 0.10 atomic percent germanium in the n-type thermoelectric elements and the p-type thermoelectric elements; and
subsequently forming dielectric material in the isolation trenches to provide field oxide of the integrated circuit.

2. The method of claim 1 , further comprising implanting a diffusion suppressant species at a dose of 1×10 14 cm −2 to 1×10 16 cm −2 in the n-type thermoelectric elements and the p-type thermoelectric elements, after forming the isolation trenches and before forming the dielectric material in the isolation trenches, the diffusion suppressant species being selected from the group consisting of fluorine and carbon.

3. The method of claim 1 , wherein subsequently implanting germanium includes implanting germanium into the n-type thermoelectric elements and the p-type thermoelectric elements with a dose sufficient to provide at least 1 atomic percent germanium in the n-type thermoelectric elements and the p-type thermoelectric elements.

4. The method of claim 1 , wherein subsequently implanting germanium includes implanting germanium into the n-type thermoelectric elements and the p-type thermoelectric elements with a dose sufficient to provide at least 3 atomic percent germanium in the n-type thermoelectric elements and the p-type thermoelectric elements.

5. The method of claim 1 , wherein subsequently implanting germanium includes implanting germanium into the n-type thermoelectric elements and the p-type thermoelectric elements by a blanket implant process which implants the germanium into the substrate across the area for the CMOS transistors.

6. The method of claim 1 , further comprising:
forming a germanium implant mask over the substrate so as to cover the area for the CMOS transistors, after forming the isolation trenches and before implanting the germanium; and
removing the germanium implant mask after implanting the germanium and before forming the dielectric material in the isolation trenches.

7. The method of claim 6 , further comprising removing semiconductor material from the substrate at bottom surfaces of the isolation trenches in the area for the embedded thermoelectric device, after implanting the germanium and before removing the germanium implant mask.

8. The method of claim 6 , wherein the germanium implant mask exposes the n-type thermoelectric elements and covers the p-type thermoelectric elements, and further comprising implanting n-type dopants into the n-type thermoelectric elements while the germanium implant mask is in place.

9. The method of claim 6 , wherein the germanium implant mask exposes the p-type thermoelectric elements and covers the n-type thermoelectric elements, and further comprising implanting p-type dopants into the p-type thermoelectric elements while the germanium implant mask is in place.

10. A method of forming an integrated circuit, the method comprising:
providing a substrate comprising silicon-based semiconductor material;
forming isolation trenches in the substrate, the substrate between the isolation trenches providing active areas of the integrated circuit, the active areas including active areas for an NMOS transistor and a PMOS transistor in an area for CMOS transistors of the integrated circuit, and for n-type thermoelectric elements and p-type thermoelectric elements of an embedded thermoelectric device of the integrated circuit, the n-type thermoelectric elements and the p-type thermoelectric elements being less than 300 nanometers wide at a narrowest position;
forming dielectric material in the isolation trenches to provide field oxide of the integrated circuit; and
implanting germanium into the n-type thermoelectric elements and the p-type thermoelectric elements with a dose sufficient to provide at least 0.10 atomic percent germanium in the n-type thermoelectric elements and the p-type thermoelectric elements.

11. The method of claim 10 , wherein implanting germanium into the n-type thermoelectric elements and the p-type thermoelectric elements is performed prior to forming the isolation trenches.

12. The method of claim 10 , wherein implanting germanium into the n-type thermoelectric elements and the p-type thermoelectric elements is performed after forming the dielectric material in the isolation trenches.

13. The method of claim 10 , further comprising:
forming a germanium implant mask over the substrate so as to cover the area for the CMOS transistors, before implanting the germanium; and
removing the germanium implant mask after implanting the germanium.

14. The method of claim 13 , wherein the germanium implant mask includes blocking elements in the area for the embedded thermoelectric device so as to block the germanium from the substrate between adjacent instances of the n-type thermoelectric elements and adjacent instances of the p-type thermoelectric elements.

Assignees

• Texas Instruments Inc

Inventors

• Edwards Henry Litzmann
• Tran Toan
• Debord Jeffrey R
• Parikh Ashesh
• Sucher Bradley David

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L21/26513

  Electricity · mapped topic

• H01L27/0617

  Electricity · mapped topic