Integrated thermoelectric generator

Patent metadata

Field	Value
Publication number	US-9490415-B2
Application number	US-201514930204-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Jul 13, 2011
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.

First claim

What is claimed is:

1. An integrated circuit comprising:
a semiconductor substrate comprising a first zone and a second zone; and
a thermoelectric generator formed at a surface of the semiconductor substrate, the thermoelectric generator comprising:
a plurality of trenches in the semiconductor substrate extending along parallel lines between the first zone and the second zone,
a plurality of ridges in the semiconductor substrate extending along parallel lines between the first zone and the second zone, each ridge of the plurality of ridges being separated from a nearest ridge of the plurality of ridges by a trench of the plurality of trenches and having a doped conductivity,
a first insulating layer in the plurality of trenches and on a top surface of the plurality of ridges,
a second insulating layer on a top surface of the first insulating layer,
an insulating coating on a top surface of the second insulating layer,
a first plurality of vias extending to the plurality of ridges in the first insulating layer, the second insulating layer, and the insulating coating, and
a patterned metallization overlying the insulating coating and electrically coupled to the plurality of ridges through the first plurality of vias, wherein
each ridge of the plurality of ridges has a current path from a first end adjacent the first zone to a second end adjacent the second zone, and
the current path of each ridge of the plurality of ridges is coupled in electrical series through the first plurality of vias and the patterned metallization.

2. The integrated circuit of claim 1 , wherein the thermoelectric generator further comprises:
a plurality of semiconductor lines extending along parallel lines between the first zone and the second zone, each semiconductor line of the plurality of semiconductor lines having a first conductivity type and being formed in a trench of the plurality of trenches and separated from the semiconductor substrate by the first insulating layer, wherein the doped conductivity of the plurality of ridges comprises a second conductivity type that is opposite the first conductivity type; and
a second plurality of vias extending to the plurality of semiconductor lines in the first insulating layer, the second insulating layer, and the insulating coating, wherein
the patterned metallization is electrically coupled to the plurality of semiconductor lines through the second plurality of vias,
each semiconductor line of the plurality of semiconductor lines has a current path from a first end adjacent the first zone to a second end adjacent the second zone, and
the current path of each ridge of the plurality of ridges and the current path of each semiconductor line of the plurality of semiconductor lines are coupled in electrical series, alternating between the current path of a semiconductor line of the plurality of semiconductor lines and the current path of a ridge of the plurality of ridges, through the first plurality of vias, the second plurality of vias, and the patterned metallization.

3. The integrated circuit of claim 1 , wherein:
the doped conductivity of the plurality of ridges comprises a first conductivity type and a second conductivity type that is opposite the first conductivity type;
each ridge of the plurality of ridges has either the first conductivity type or the second conductivity type; and
for each ridge of the plurality of ridges with the first conductivity type, a nearest ridge of the plurality of ridges has the second conductivity type.

4. The integrated circuit of claim 1 , further comprising a plurality of non-volatile memory cells disposed in the semiconductor substrate.

5. The integrated circuit of claim 1 , wherein the first insulating layer comprises an oxide.

6. The integrated circuit of claim 5 , wherein the second insulating layer comprises a nitride.

7. The integrated circuit of claim 6 , wherein the insulating coating comprises an oxide.

8. An integrated circuit comprising:
a semiconductor substrate comprising a first zone and a second zone; and
a thermoelectric generator formed at a surface of the semiconductor substrate, the thermoelectric generator comprising:
a plurality of trenches in the semiconductor substrate extending along parallel lines between the first zone and the second zone,
a plurality of ridges in the semiconductor substrate extending along parallel lines between the first zone and the second zone, each ridge of the plurality of ridges being separated from a nearest ridge of the plurality of ridges by a trench of the plurality of trenches and having a doped conductivity,
a first insulating layer in the plurality of trenches and on a top surface of the plurality of ridges,
a plurality of thermocouple structures on the first insulating layer, each thermocouple structure of the plurality of thermocouple structures comprising
a first semiconductor line having a first conductivity type,
a second semiconductor line having a second conductivity type opposite the first conductivity type, the first semiconductor line and the second semiconductor line extending along parallel lines between the first zone and the second zone, and
an insulating encasement separating the first semiconductor line from the second semiconductor line, the insulating encasement in contact with sidewalls of the first semiconductor line and in contact with sidewalls of the second semiconductor line,

a first plurality of vias extending to the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures,
a second plurality of vias extending to the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures, and
a patterned metallization overlying the plurality of thermocouple structures and electrically coupled to the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures through the first plurality of vias and to the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures through the second plurality of vias, wherein
the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures has a current path from a first end adjacent the first zone to a second end adjacent the second zone,
the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures has a current path from a first end adjacent the first zone to a second end adjacent the second zone, and
the current path of the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures and the current path of the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures are coupled in electrical series, alternating between the current path of a first semiconductor line of a thermocouple structure of the plurality of thermocouple structures and the current path of a second semiconductor line of a thermocouple structure of the plurality of thermocouple structures, through the first plurality of vias, the second plurality of vias, and the patterned metallization.

9. The integrated circuit of claim 8 , wherein the first semiconductor line is directly above the second semiconductor line.

10. The integrated circuit of claim 8 , wherein:
each trench of the plurality of trenches comprises a third semiconductor line extending between the first zone and the second zone, having the second conductivity type, and being separated from the semiconductor substrate by the first insulating layer, wherein the doped conductivity of the plurality of ridges comprises the first conductivity type; and
the thermoe

Assignees

• Stmicroelectronics Rousset

Inventors

• Fornara Pascal
• Rivero Christian

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/16

  Electricity · mapped topic

• H01L35/32 Primary

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic