Selecting optimum primary and secondary parameters to calibrate and generate an unbiased forecasting model
US-12020124-B2 · Jun 25, 2024 · US
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Parikh Ashesh patents
Parikh Ashesh is listed as an inventor on 12 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Parikh Ashesh |
| Total patents | 12 |
| First publication | Jul 2, 2015 |
| Latest publication | Jun 25, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Network optimization
US-11775852-B2 · Oct 3, 2023 · US
Selecting optimum primary and secondary parameters to calibrate and generate an unbiased forecasting model
US-2021216907-A1 · Jul 15, 2021 · US
Network optimization
US-2021065031-A1 · Mar 4, 2021 · US
Method to improve transistor matching
US-10339251-B2 · Jul 2, 2019 · US
CMOS-based thermopile with reduced thermal conductance
US-9853086-B2 · Dec 26, 2017 · US
Method to improve transistor matching
US-2017228488-A1 · Aug 10, 2017 · US
Method to improve transistor matching
US-9665675-B2 · May 30, 2017 · US
Cmos-based thermopile with reduced thermal conductance
US-2017062518-A1 · Mar 2, 2017 · US
CMOS-based thermopile with reduced thermal conductance
US-9496313-B2 · Nov 15, 2016 · US
Recent patents
Latest publications not already listed above.
Cmos-based thermopile with reduced thermal conductance
US-2015349022-A1 · Dec 3, 2015 · US
Method to improve transistor matching
US-2015187655-A1 · Jul 2, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Texas Instruments Inc | 8 |
| Accenture Global Solutions Ltd | 4 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 8 |
| H10P30/208 | 4 |
| H10P30/204 | 4 |
| H10P30/21 | 4 |
| H01L27/16 | 4 |