Apparatus, system, and method for on-chip thermoelectricity generation

Patent metadata

Field	Value
Publication number	US-9515245-B2
Application number	US-201113185794-A
Country	US
Kind code	B2
Filing date	Jul 19, 2011
Priority date	Jul 23, 2010
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An apparatus, system, and method for a thermoelectric generator. In some embodiments, the thermoelectric generator comprises a first thermoelectric region and a second thermoelectric region, where the second thermoelectric region may be coupled to the first thermoelectric region by a first conductor. In some embodiments, a second conductor may be coupled to the first thermoelectric region and a third conductor may be coupled to the second thermoelectric region. In some embodiments, the first conductor may be in a first plane, the first thermoelectric region and the second thermoelectric region may be in a second plane, and the second conductor and the third conductor may be in a third plane.

First claim

What is claimed is:

1. A thermoelectric device, comprising:
a first thermoelectric region;
a second thermoelectric region, wherein the first thermoelectric region and the second thermoelectric region are configured to generate electric current when there is a thermal difference between the first thermoelectric region and the second thermoelectric region;
a first conductor having a bottom surface directly abutting a top surface of a substrate, the first conductor coupling the first thermoelectric region to the second thermoelectric region;
a second conductor coupled to the first thermoelectric region;
a third conductor coupled to the second thermoelectric region;
a fourth conductor directly connected to a top surface of the second conductor and a top surface of the substrate, the fourth conductor coupling the second conductor to the substrate; and
a fifth conductor directly connected to a top surface of the third conductor and a top surface of the substrate, the fifth conductor coupling the third conductor to the substrate,
wherein the substrate comprises a heat source, the thermoelectric device being fabricated directly on top of the heat source, and
wherein the second conductor and the third conductor are configured to deliver, via the fourth and fifth conductors, respectively, the generated electric current from the first thermoelectric region and the second thermoelectric region to a power control module.

2. The thermoelectric device of claim 1 , where the second and third conductors are coupled to an integrated circuit.

3. The thermoelectric device of claim 2 , wherein heat generated during operation of the integrated circuit directly heats at least one of the first thermoelectric region and the second thermoelectric region to create a thermal difference between the first thermoelectric region and the second thermoelectric region and to produce electric current.

4. The thermoelectric device of claim 1 , where the first, second and third conductors are metal.

5. The thermoelectric device of claim 4 , where at least one of the first, second, and third conductor is copper or another conductive metal.

6. The thermoelectric device of claim 1 , where the first thermoelectric region is a semiconductor, the second thermoelectric region is a semiconductor, and wherein the first thermoelectric region and the second thermoelectric region comprise Bismuth Telluride.

7. The thermoelectric device of claim 6 , where at least one of the first thermoelectric region and the second thermoelectric region is n-doped.

8. The thermoelectric device of claim 6 , where at least one of the first thermoelectric region and the second thermoelectric region is p-doped.

9. The thermoelectric device of claim 1 , where:
the first conductor is in a first plane, the first plane defined as a plane parallel to a surface of the first conductor contacting the first thermoelectric region;
the first thermoelectric region and the second thermoelectric region are in a second plane, where the second plane is approximately parallel to the first plane, the second plane defined as a plane parallel to a surface of the first thermoelectric region and the second thermoelectric region contacting the first conductor;
the second conductor and the third conductor are in a third plane, where the third plane is approximately parallel to the first plane, the third plane defined as a plane parallel to a surface of the second conductor contacting the first thermoelectric region.

10. The thermoelectric device of claim 9 , where the first plane is adjacent to the second plane and the second plane is adjacent to the third plane.

11. The thermoelectric device of claim 9 , where the first conductor is coupled to the first thermoelectric region on a first surface, where the first surface of the thermoelectric region is between the first plane and the second plane.

12. The thermoelectric device of claim 9 , where the second conductor is coupled to the first thermoelectric region on a second surface of the first thermoelectric region, where the second surface of the thermoelectric region is between the second plane and the third plane.

13. The thermoelectric device of claim 9 , where the first conductor is coupled to the second thermoelectric region on a first surface of the second thermoelectric region, where the first surface of the thermoelectric region is between the first plane and the second plane.

14. The thermoelectric device of claim 9 , where the third conductor is coupled to the second thermoelectric region on a second surface of the second thermoelectric region, where the second surface of the thermoelectric region is between the second plane and the third plane.

15. A semiconductor device, comprising:
an integrated circuit;
a first thermoelectric region;
a second thermoelectric region, wherein the second thermoelectric region is coupled to the first thermoelectric region by a first conductor having a bottom surface directly abutting a top surface of a substrate, and wherein the first thermoelectric region and the second thermoelectric region are configured to generate electric current when there is a thermal difference between the first thermoelectric region and the second thermoelectric region;
a second conductor coupled to the first thermoelectric region;
a third conductor coupled to the second thermoelectric region;
a fourth conductor directly connected to a top surface of the second conductor and a top surface of the substrate, the fourth conductor coupling the second conductor to the substrate; and
a fifth conductor directly connected to a top surface of the third conductor and a top surface of the substrate, the fifth conductor coupling the third conductor to the substrate, wherein the substrate comprises a heat source, the thermoelectric device being fabricated directly on top of the heat source,
where the first thermoelectric region and the second thermoelectric region are thermally coupled to the integrated circuit, and
wherein the second conductor and the third conductor are configured to deliver, via the fourth and fifth conductors, respectively, the generated current by the first thermoelectric region and the second thermoelectric region to a power control module.

16. The semiconductor device of claim 15 , where the first thermoelectric region and the second thermoelectric region are configured to provide electrical current to the integrated circuit.

17. The semiconductor device of claim 15 , where:
the first conductor is in a first plane, the first plane defined as a plane parallel to a surface of the first conductor contacting the first thermoelectric region;
the first thermoelectric region and the second thermoelectric region are in a second plane, where the second plane is approximately parallel to the first plane, the second plane defined as a plane parallel to a surface of the first thermoelectric region and the second thermoelectric region contacting the first conductor;
the second conductor and the third conductor are in a third plane, where the third plane is approximately parallel to the first plane, the third plane defined as a plane parallel to a surface of the second conductor contacting the first thermoelectric region; and
the integrated circuit is in a fourth plane, where the fourth plane is approximately parallel to the first plane, the fourth plane defined as a plane parallel to a surface of the integrated circuit facing the first thermoelectric region.

18. The semiconductor device of claim 17 , where the integrated circuit is thermally coupled to the fi

Assignees

• Hussain Muhammad M
• Fahad Hossain M
• Rojas Jhonathan P
• Univ King Abdullah Sci & Tech

Inventors

• Hussain Muhammad M
• Fahad Hossain M
• Rojas Jhonathan P

Classifications

• H10W40/28

  comprising Peltier coolers · CPC title

• H01L35/32 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L27/16

  Electricity · mapped topic