CMOS-based thermopile with reduced thermal conductance

Patent metadata

Field	Value
Publication number	US-9496313-B2
Application number	US-201414292198-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate comprising a single-crystal silicon wafer;
field oxide in isolation trenches in the substrate, the field oxide providing lateral isolation for an n-channel metal oxide semiconductor (NMOS) transistor and a p-channel metal oxide semiconductor (PMOS) transistor in an area for complementary metal oxide semiconductor (CMOS) transistors of the integrated circuit, and providing lateral isolation for n-type thermoelectric elements and p-type thermoelectric elements of an embedded thermoelectric device of the integrated circuit;
a metal interconnect structure which connects upper ends of the n-type thermoelectric elements and the p-type thermoelectric elements to a thermal node; and
a germanium implanted region in the substrate encompassing the n-type thermoelectric elements and the p-type thermoelectric elements, the germanium implanted region having at least 0.10 atomic percent germanium in the n-type thermoelectric elements and the p-type thermoelectric elements, wherein the germanium implanted region extends approximately as deep in the substrate as the field oxide.

2. The integrated circuit of claim 1 , wherein the germanium implanted region having at least 1 atomic percent germanium in the n-type thermoelectric elements and the p-type thermoelectric elements.

3. The integrated circuit of claim 1 , wherein the germanium implanted region having at least 3 atomic percent germanium in the n-type thermoelectric elements and the p-type thermoelectric elements.

4. The integrated circuit of claim 1 , wherein the germanium implanted region extends across the area for the CMOS transistors.

5. The integrated circuit of claim 1 , wherein the germanium implanted region includes a diffusion suppressant species with a density of at least 1×10 20 cm −3 in the n-type thermoelectric elements and the p-type thermoelectric elements, the diffusion suppressant species being selected from the group consisting of fluorine and carbon.

Assignees

• Texas Instruments Inc

Inventors

• Edwards Henry Litzmann
• Tran Toan
• Debord Jeffrey R
• Parikh Ashesh
• Sucher Bradley David

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0188 Primary

  Manufacturing their isolation regions · CPC title