Semiconductor device contact structure having stacked nickel, copper, and tin layers

Patent metadata

Field	Value
Publication number	US-9853006-B2
Application number	US-201615191723-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Aug 25, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

First claim

The invention claimed is:

1. A semiconductor device fabrication method comprising:
forming a barrier layer upon a dielectric layer, the barrier layer being a TiW layer;
forming an electrically conductive plating layer upon the barrier layer, the plating layer being composed of Cu; and
forming a multilayered contact upon the plating layer by plating a Nickel layer upon the plating layer, plating a Copper layer upon the Nickel layer, and plating a Tin layer upon the Copper layer; and
heat treating the multilayered contact to reflow the Tin layer with the Copper layer to form a Copper-Tin layer,
wherein the heat treating fully converts the Copper layer into the Copper-Tin layer such that the Copper-Tin layer is directly upon the Nickel layer; and
the heat treating partially converts the Tin layer into the Copper-Tin layer such that a remaining portion of the Tin layer is retained upon the Copper-Tin layer, and
further comprising forming solder on the remaining portion of the Tin layer.

2. The semiconductor device fabrication method of claim 1 , further comprising:
heat treating the multilayered contact to at least partially reflow the Tin layer with the Copper layer to form a Copper-Tin layer.

3. The semiconductor device fabrication method of claim 2 , wherein the heat treating fully converts the Copper layer into the Copper-Tin layer such that the Copper-Tin layer is directly upon the Nickel layer.

4. The semiconductor device fabrication method of claim 2 , wherein a portion of the Tin layer is retained upon the Copper-Tin layer.

5. The semiconductor device fabrication method of claim 1 , further comprising:
attaching a handler wafer to the multilayered contact side of the semiconductor device with adhesive.

6. The semiconductor device fabrication method of claim 1 , further comprising: forming a photoresist upon the conductive layer;
forming a contact trench in the photoresist layer, the contact trench exposing a portion of the conductive layer;
forming the multilayered contact structure within the contact trench, and;
removing the photoresist.

7. The semiconductor device fabrication method of claim 1 , further comprising:
removing portions of the conductive layer exterior to the multilayered contact structure, such that sidewalls of the conductive layer are coplanar with sidewalls of the Nickel layer, sidewalls of the Copper layer, and sidewalls of the Tin layer of the multilayered contact.

8. The semiconductor device fabrication method of claim 1 , further comprising:
removing portions of the barrier layer exterior to the multilayered contact structure, such that sidewalls of the barrier layer are coplanar with sidewalls of the Nickel layer, sidewalls of the Copper layer, and sidewalls of the Tin layer of the multilayered contact.

9. The semiconductor device fabrication method of claim 1 , wherein the multilayered contact is a capture pad.

10. The semiconductor device fabrication method of claim 1 , wherein the semiconductor device is a thinned die and wherein at least one layer of the multilayer contact is wettable to solder electrically connected to a second die in a three dimensional package.

11. The semiconductor device fabrication method of claim 1 , wherein:
the barrier layer has a thickness in a range of 0.125 microns to 0.205 microns;
the plating layer has a thickness in a range of 0.1 microns to 0.6 microns;
the Nickel layer has a thickness of 2 microns,
the Copper layer has a thickness of 1 micron, and
the Tin layer has a thickness of 1.5 microns.

12. The semiconductor device fabrication method of claim 1 , further comprising forming a metal interconnect and a metal line in the dielectric layer using damascene and deposition processes,
wherein the barrier layer directly contacts a via formed in the dielectric layer;
the via contacts one of the metal lines; and
the dielectric layer is formed on a semiconductor substrate.

13. The semiconductor device fabrication method of claim 1 , wherein the multi-layered contact is part of a chip and is devoid of solder, and further comprising forming solder on a package substrate prior to joining the multilayer contact to the solder.

14. The semiconductor device fabrication method of claim 1 , wherein:
the Copper-Tin layer is 2 microns thick; and
the remaining portion of the Tin layer is 0.5 microns thick.

15. The semiconductor device fabrication method of claim 1 , further comprising forming a metal interconnect and a metal line in the dielectric layer using damascene and deposition processes,
wherein the barrier layer directly contacts a via formed in the dielectric layer;
the via contacts one of the metal lines; and
the dielectric layer is formed on a semiconductor substrate.

16. A semiconductor device :fabrication method comprising:
forming a barrier layer upon a dielectric layer, the barrier layer being a TiW layer;
forming an electrically conductive plating layer upon the barrier layer, the plating layer being composed of Cu;
forming a multilayered contact upon the plating layer by plating a Nickel layer upon the plating layer. plating a Copper layer upon the Nickel layer, and plating a Tin layer upon the Copper layer; and
heat treating the multilayered contact to reflow the Tin layer with the Copper layer to form a Copper-Tin layer,
wherein the heat treating fully converts the Copper layer into the Copper-Tin layer such that the Copper-Tin layer is directly upon the Nickel layer;
the heat treating partially converts the Tin layer into the Copper-Tin layer such that a remaining portion of the Tin layer is retained upon the Copper-Tin layer;
the TiW layer is 0.125 microns to 0.205 microns thick;
the plating layer is 0.1 microns to 0.6 microns thick;
the Nickel layer is 2 microns thick;
the Copper-Tin layer is 2 microns thick; and
the remaining portion of the Tin layer is 0.5 microns thick.

17. A semiconductor device fabrication method comprising:
forming a barrier layer upon a dielectric layer. the barrier layer being a TiW layer;
forming an electrically conductive plating layer upon the barrier layer, the plating layer being composed of Cu;
forming a multilayered contact upon the plating layer by plating a Nickel layer upon the plating layer. plating a Copper layer upon the Nickel layer, and plating a Tin layer upon the Copper layer; and
heat treating the multilayered contact to reflow the Tin layer with the Copper layer to form a Copper-Tin layer,
wherein the heat treating fully converts the Copper layer into the Copper-Tin layer such that the Copper-Tin layer is directly upon the Nickel layer;
the heat treating partially converts the Tin layer into the Copper-Tin layer such that a remaining portion of the Tin layer is retained upon the Copper-Tin laver; and
the Copper-Tin layer is a Cu 6 Sn 3 layer.

Assignees

• Globalfoundries Inc

Inventors

• Arvin Charles L
• Cox Harry D
• Perfecto Eric D
• Wassick Thomas A

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/019

  of bond pads · CPC title