Non-planar transistors with replacement fins and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9543209-B2
Application number	US-201514864037-A
Country	US
Kind code	B2
Filing date	Sep 24, 2015
Priority date	Jun 21, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A method includes forming a first semiconductor fin, and oxidizing surface portions of the first semiconductor fin to form a first oxide layer. The first oxide layer includes a top portion overlapping the first semiconductor fin and sidewall portions on sidewalls of the first semiconductor fin. The top portion of the first oxide layer is then removed, wherein the sidewall portions of the first oxide layer remains after the removing. The top portion of the first semiconductor fin is removed to form a recess between the sidewall portions of the first oxide layer. An epitaxy is performed to grow a semiconductor region in the recess.

First claim

What is claimed is:

1. A method comprising:
forming a first, a second, and a third semiconductor fin;
simultaneously oxidizing sidewall portions of the first, the second, and the third semiconductor fins to form a first, a second, and a third oxide layer, respectively;
replacing a top portion of the first semiconductor fin with a first replacement fin;
replacing a top portion of the second semiconductor fin with a second replacement fin;
removing the first and the second oxide layers without removing the third oxide layer;
forming a first gate dielectric on a top surface and sidewalls of the first replacement fin;
forming a second gate dielectric on a top surface and sidewalls of the second replacement fin; and
forming a third gate dielectric on a top surface and sidewalls of the third oxide layer.

2. The method of claim 1 , wherein the replacing the top portion of the first semiconductor fin comprises:
removing a top portion of the first oxide layer, wherein sidewall portions of the first oxide layer remain after the removing;
etching the top portion of the first semiconductor fin to form a recess between the sidewall portions of the first oxide layer; and
epitaxially growing the first replacement fin in the recess.

3. The method of claim 1 further comprising:
forming a hard mask layer to cover the first, the second, and the third oxide layers; and
performing a lithography step to form an opening in the hard mask layer, wherein the first oxide layer is exposed to the opening.

4. The method of claim 3 further comprising:
forming an additional oxide layer over the hard mask layer; and
performing a planarization to remove portions of the additional oxide layer that are higher than a top surface of the hard mask layer, wherein the top surface of the hard mask layer is level with top surfaces of remaining portions of the additional oxide layer.

5. The method of claim 1 , wherein the oxidizing comprises a thermal oxidation.

6. The method of claim 5 , wherein the thermal oxidation is performed at a temperature higher than about 800° C.

7. The method of claim 1 further comprising forming a gate electrode on each of the first gate dielectric, the second gate dielectric, and the third gate dielectric.

8. A method comprising:
forming a silicon fin protruding higher than Shallow Trench Isolation (STI) regions, wherein the STI regions comprise portions on opposite sides of the silicon fin;
oxidizing a top surface portion and sidewall surface portions of the silicon fin to form a first silicon oxide layer;
forming a mask layer comprising:
sidewall portions on sidewalls of the first silicon oxide layer; and
a top portion overlapping the first silicon oxide layer;

forming a second silicon oxide layer filling recesses that extend into the mask layer, wherein a top portion of the mask layer that overlaps the silicon fin is exposed;
etching the top portion of the mask layer and a top portion of the first silicon oxide layer to expose the silicon fin;
removing a top portion of the silicon fin to form a recess; and
re-growing a replacement fin in the recess.

9. The method of claim 8 further comprising, after the replacement fin is formed, removing remaining portions of the first silicon oxide layer.

10. The method of claim 8 further comprising, after the replacement fin is formed, removing remaining portions of the second silicon oxide layer.

11. The method of claim 8 , wherein the forming the second silicon oxide layer and the forming the mask layer comprises a Chemical Mechanical Polish (CMP).

12. The method of claim 8 further comprising:
forming a gate dielectric over the silicon fin; and
forming a gate electrode over the gate dielectric.

13. The method of claim 8 , wherein the recess is defined by opposite portions of the first silicon oxide layer.

14. The method of claim 8 , wherein the replacement fin comprises a material different from silicon.

15. A method comprising:
forming a first, a second, and a third semiconductor fin;
oxidizing sidewall portions of the first, the second, and the third semiconductor fins to form a first, a second, and a third oxide layer, respectively;
replacing a top portion of the first semiconductor fin with a first replacement fin, wherein the replacing the top portion of the first semiconductor fin comprises:
removing a top portion of the first oxide layer covering the first semiconductor fin;
etching the top portion of the first semiconductor fin to form a recess between remaining sidewall portions of the first oxide layer; and
growing the first replacement fin in the recess;

replacing a top portion of the second semiconductor fin with a second replacement fin;
removing the first and the second oxide layers without removing the third oxide layer;
forming a first gate dielectric on a top surface and sidewalls of the first replacement fin;
forming a second gate dielectric on a top surface and sidewalls of the second replacement fin; and
forming a third gate dielectric on a top surface and sidewalls of the third oxide layer.

16. The method of claim 15 further comprising:
forming a hard mask layer to cover the first, the second, and the third oxide layers; and
performing a lithography step to form an opening in the hard mask layer, wherein the top portion of the first oxide layer is removed through the opening.

17. The method of claim 16 further comprising:
forming an additional oxide layer over the hard mask layer; and
performing a planarization to remove portions of the additional oxide layer that are higher than a top surface of the hard mask layer, wherein the top surface of the hard mask layer is level with top surfaces of remaining portions of the additional oxide layer.

18. The method of claim 15 , wherein the oxidizing comprises a thermal oxidation.

19. The method of claim 18 , wherein the thermal oxidation is performed at a temperature higher than about 800° C.

20. The method of claim 15 further comprising forming a gate electrode on each of the first gate dielectric, the second gate dielectric, and the third gate dielectric.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fung Ka-Hing

Classifications

• H01L29/7853

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L21/823412 Primary

  Electricity · mapped topic