Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings

Patent metadata

Field	Value
Publication number	US-9305883-B2
Application number	US-201514620233-A
Country	US
Kind code	B2
Filing date	Feb 12, 2015
Priority date	Sep 6, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.

First claim

What is claimed is:

1. A finFET including a gate and a source/drain (S/D) region formed on a substrate, the gate formed over at least two fins, said at least two fins extending into said S/D region, the finFET further comprising:
facing sidewalls of said at least two fins within said S/D region, first epitaxial material formed on a first of said facing sidewalls, and second epitaxial material formed on a second of said facing sidewalls, wherein each of said first epitaxial material and said second epitaxial material include a faceted upper surface sloping from the associated sidewall toward said substrate;
a dielectric material disposed on said substrate between said facing sidewalls such that said dielectric material covers a lower portion of both said upper surfaces; and
a bar conductively connected to an upper portion of both said upper surfaces.

2. The finFET of claim 1 , wherein said bar extends parallel to said gate, and a region of said dielectric material extends parallel to and between said gate and said bar.

3. The finFET of claim 1 , wherein said first and second epitaxial materials do not directly contact each other.

4. The finFET of claim 1 , wherein said gate includes a first spacer and wherein both of said upper surfaces has an edge abutting said first spacer and further comprising:
a reinforcing spacer formed over the gate and covering said edge.

5. The finFET of claim 1 , wherein said bar includes a metal silicide.

6. The finFET of claim 5 , further comprising:
a silicon layer between said bar and at least one said upper surfaces.

7. The finFET of claim 1 , wherein said first epitaxial material comprises boron doped SiGe or phosphorous doped Si.

8. A finFET including a gate and a source/drain (S/D) region formed on a substrate, the gate formed over a set of fins, wherein said gate includes a first spacer and at least three of said fins extend into said S/D region, the finFET further comprising:
first epitaxial material formed on facing sidewalls of a first adjacent pair of said set within said S/D region, and second epitaxial material formed on facing sidewalls of a second adjacent pair of said set within said S/D region, where said second adjacent pair includes at least one of said set that is not part of said first adjacent pair;
a contact conductively connecting said first epitaxial material to said second epitaxial material, said contact spaced from said first spacer by a dielectric region, wherein said first epitaxial material comprises SiGe and a silicon layer is between said contact and said first epitaxial material.

9. The finFET of claim 8 , wherein said gate includes a second spacer between said first spacer and said contact, wherein said second spacer vertically extends from the height of the gate to the top surface of said first epitaxial material.

10. The finFET of claim 9 , wherein said contact comprises silicide, and said silicide is spaced from said gate by three layers that include said first spacer, said second spacer, and a region of dielectric oxide.

11. The finFET of claim 9 , wherein said second spacer covers a gate-adjacent edge of said first epitaxial material.

Assignees

• Globalfoundries Inc

Inventors

• Naczas Sebastian
• Paruchuri Vamsi
• Reznicek Alexander
• Schepis Dominic J

Classifications

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title