Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts

Patent metadata

Field	Value
Publication number	US-9530866-B1
Application number	US-201615097621-A
Country	US
Kind code	B1
Filing date	Apr 13, 2016
Priority date	Apr 13, 2016
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

Forming a first sidewall spacer adjacent a vertically oriented channel semiconductor structure (“VCS structure’) and adjacent a cap layer, performing at least one planarization process so as to planarize an insulating material and expose an upper surface of the cap layer and an upper surface of the first spacer and removing a portion of the first spacer and an entirety of the cap layer so as to thereby expose an upper surface of the VCS structure and define a spacer/contact cavity above the VCS structure and the first spacer. The method also includes forming a second spacer in the spacer/contact cavity, forming a top source/drain region in the VCS structure and forming a top source/drain contact within the spacer/contact cavity that is conductively coupled to the top source/drain region, wherein the conductive contact physically contacts the second spacer in the spacer/contact cavity.

First claim

What is claimed:

1. A method of forming a vertical transistor device, the method comprising:
forming a vertically oriented channel semiconductor structure with a cap layer positioned above said vertically oriented channel semiconductor structure;
forming a first sidewall spacer adjacent said vertically oriented channel semiconductor structure and adjacent said cap layer;
forming a layer of insulating material adjacent said first sidewall spacer;
performing at least one planarization process so as to planarize an upper surface of said layer of insulating material and expose an upper surface of said cap layer and an upper surface of said first sidewall spacer;
performing at least one etching process to remove a portion of said first sidewall spacer and to remove an entirety of said cap layer so as to thereby expose an upper surface of said vertically oriented channel semiconductor structure and define a spacer/contact cavity above said vertically oriented channel semiconductor structure and said first sidewall spacer;
forming a second spacer in said spacer/contact cavity, wherein after formation of said second spacer, at least a portion of said upper surface of said vertically oriented channel semiconductor structure remains exposed;
after forming said second spacer, forming a top source/drain region in said vertically oriented channel semiconductor structure; and
forming a top source/drain contact within said spacer/contact cavity that is conductively coupled to said top source/drain region, wherein said conductive contact physically contacts said second spacer in said spacer/contact cavity.

2. The method of claim 1 , wherein said first sidewall spacer is formed on and in contact with a sidewall of said vertically oriented channel semiconductor structure and on and in contact with a sidewall of said cap layer.

3. The method of claim 1 , wherein said second sidewall spacer comprises a low-k insulating material.

4. The method of claim 3 , wherein the cap layer comprises silicon nitride and the first sidewall spacer comprises SiOCN.

5. The method of claim 1 , wherein, after forming said top source/drain region and prior to forming said top source/drain contact, the method comprises forming an epi semiconductor material on said exposed upper surface of said vertically oriented channel semiconductor structure.

6. The method of claim 1 , wherein forming said second spacer in said spacer/contact cavity comprises depositing a layer of material for said second spacer in said spacer/contact cavity and performing an anisotropic etching process on said layer of material for said second spacer.

7. The method of claim 1 , wherein forming said second spacer in said spacer/contact cavity comprises forming said second spacer in said spacer/contact cavity such that, after the formation of said second spacer, the entire upper surface of said vertically oriented channel semiconductor structure remains exposed.

8. The method of claim 1 , wherein forming said top source/drain region comprises performing an ion implantation process through an opening defined by said second spacer.

9. The method of claim 1 , wherein:
prior to forming said first sidewall spacer, the method comprises:
forming a layer of a bottom spacer material around said vertically oriented channel semiconductor structure; and
forming a sacrificial material layer on and in contact with an upper surface of said layer of said bottom spacer material, said sacrificial material layer having an upper surface, wherein said first sidewall spacer is formed such that a bottom surface of said first sidewall spacer contacts said upper surface of said sacrificial material layer; and

after forming said first sidewall spacer and prior to forming said layer of insulating material adjacent said first sidewall spacer, the method further comprises:
removing said sacrificial material layer so as to define a replacement gate cavity between a bottom surface of said first sidewall spacer and said layer of said bottom spacer material; and
forming a replacement gate structure in said replacement gate cavity.

10. The method of claim 9 , wherein an outer surface of said replacement gate structure is substantially vertically aligned with an outer side surface of said first sidewall spacer.

11. A method of forming a vertical transistor device, the method comprising:
forming a vertically oriented channel semiconductor structure with a cap layer positioned above said vertically oriented channel semiconductor structure;
forming a first sidewall spacer on and in contact with a sidewall of said vertically oriented channel semiconductor structure and on and in contact with a sidewall of said cap layer;
forming a layer of insulating material adjacent said first sidewall spacer;
performing at least one planarization process so as to planarize an upper surface of said layer of insulating material and expose an upper surface of said cap layer and an upper surface of said first sidewall spacer;
performing at least one etching process to remove a portion of said first sidewall spacer and to remove an entirety of said cap layer so as to thereby expose an upper surface of said vertically oriented channel semiconductor structure and define a spacer/contact cavity above said vertically oriented channel semiconductor structure and said first sidewall spacer;
forming a second spacer comprised of a low-k material in said spacer/contact cavity, wherein after formation of said second spacer, substantially the entire upper surface of said vertically oriented channel semiconductor structure remains exposed;
after forming said second spacer, forming a top source/drain region in said vertically oriented channel semiconductor structure by performing an ion implantation process through an opening defined by said second spacer; and
forming a top source/drain contact within said spacer/contact cavity that is conductively coupled to said top source/drain region, wherein said conductive contact physically contacts said second spacer in said spacer/contact cavity.

12. The method of claim 11 , wherein said cap layer comprises silicon nitride and said first sidewall spacer comprises SiOCN.

13. The method of claim 11 wherein, after forming said top source/drain region and prior to forming said top source/drain contact, the method comprises forming an epi semiconductor material on said exposed upper surface of said vertically oriented channel semiconductor structure.

14. The method of claim 11 , wherein forming said second spacer in said spacer/contact cavity comprises depositing a layer of material for said second spacer in said spacer/contact cavity and performing an anisotropic etching process on said layer of material for said second spacer.

15. The method of claim 11 wherein:
prior to forming said first sidewall spacer, the method comprises:
forming a layer of a bottom spacer material around said vertically oriented channel semiconductor structure; and
forming a sacrificial material layer on and in contact with an upper surface of said layer of said bottom spacer material, said sacrificial material layer having an upper surface, wherein said first sidewall spacer is formed such that a bottom surface of said first sidewall spacer contacts said upper surface of said sacrificial material layer; and

after forming said first sidewall spacer and prior to forming said layer of insulating material adjacent said first sidewall spacer, the method further comprises:
removing said sacrificial material layer so as to define a replacement gate cavity between a bottom surface of said first sidewall spacer and said layer

Assignees

• Globalfoundries Inc

Inventors

• Zhang John H
• Radens Carl
• Bentley Steven J
• Cohen Brian A
• Lim Kwan-Yong

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title