Integrated circuit package substrate

Patent metadata

Field	Value
Publication number	US-9831169-B2
Application number	US-201615260099-A
Country	US
Kind code	B2
Filing date	Sep 8, 2016
Priority date	Oct 16, 2013
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A method of forming an integrated circuit (IC) package substrate comprising:
depositing a first surface finish on one or more lands disposed on a first side of the package substrate, wherein the first side is disposed opposite a second side of the substrate; and
depositing a second surface finish on one or more electrical routing features embedded in a die interconnect region disposed on the second side of the package substrate, the second surface finish being in direct contact with the one or more electrical routing features, wherein the electrical routing features are to bond with die interconnect structures of one or more dies, and wherein the second surface finish has a different chemical composition than the first surface finish.

2. The method of claim 1 , wherein the depositing of the first surface finish is accomplished by a Direct Immersion Gold (DIG) process.

3. The method of claim 1 , wherein the depositing of the first surface finish is accomplished by an Electroless Palladium Immersion Gold (EPIG) process.

4. The method of claim 1 , wherein the depositing of the first surface finish is accomplished by an Organic Solderability Preservative (OSP) process.

5. The method of claim 1 , wherein depositing the second surface finish is accomplished using an electroless plating process.

6. The method of claim 1 , wherein depositing the second surface finish includes depositing nickel (Ni).

7. The method of claim 6 , wherein depositing the second surface finish includes depositing one or both of palladium or gold.

8. The method of claim 7 , wherein depositing the second surface finish includes depositing gold using an electroless nickel-immersion gold (ENIG+EG) process.

9. The method of claim 1 , wherein depositing the second surface finish includes depositing imidazole or an imidazole derivative.

10. The method of claim 1 , wherein, after deposition, the second surface finish has a thickness of less than or equal to 500 nanometers.

11. The method of claim 1 , wherein depositing the first surface finish includes depositing nickel (Ni).

12. The method of claim 1 , wherein depositing the first surface finish includes depositing one or both of palladium or gold.

13. The method of claim 1 , further comprising:
depositing a first lamination layer on the second side of the package substrate, before depositing the first surface finish, wherein the first lamination layer is to prevent deposition of the first surface finish on the one or more electrical routing features disposed on the second side; and
removing the first lamination layer from the second side of the package substrate to expose the one or more electrical routing features disposed on the second side.

14. The method of claim 1 , further comprising:
depositing a second lamination layer on the first side of the package substrate, before depositing the second surface finish, wherein the second lamination layer is to prevent deposition of the second surface finish on the one or more lands disposed on the first side; and
removing the second lamination layer from the first side of the package substrate.

15. The method of claim 1 , wherein the electrical routing features include die bond pads.

Assignees

• Intel Corp

Inventors

• Zhang Qinglei
• Lotz Stefanie M

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title