Integrated circuit package with embedded bridge

Patent metadata

Field	Value
Publication number	US-2016155705-A1
Application number	US-201615004774-A
Country	US
Kind code	A1
Filing date	Jan 22, 2016
Priority date	Dec 18, 2013
Publication date	Jun 2, 2016
Grant date	—

Abstract

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

First claim

1 - 14 . (canceled)

15 . A method of assembling an integrated circuit package comprising:
coupling a first die to a bridge by bonding a portion of a first plurality of input/output (I/O) interconnect structures disposed on the first die to a first plurality of electrical routing features disposed on the bridge; coupling a second die to the bridge by bonding a portion of a second plurality of I/O interconnect structures disposed on the second die to a second plurality of electrical routing features disposed on the bridge, wherein the first and second plurality of electrical routing features are disposed on a first side of the bridge, and wherein the bridge has a third plurality of routing features disposed on a second side, opposite the first side, configured to route electrical signals between the second side and the first side; and depositing an electrically insulating material over the first die, the second die, and the bridge to at least partially embed the first die, the second die, and the bridge in the electrically insulating material.

16 . The method of claim 15 , further comprising coupling the first die and the second die to a carrier prior to the coupling of the first die and second die to the bridge.

17 . The method of claim 16 , wherein the carrier is a heat spreader.

18 . The method of claim 15 , further comprising coupling a die stack with the bridge by bonding a third plurality of I/O interconnect structures of the die stack to the third electrical routing features disposed on the bridge.

19 . The method of claim 15 , wherein depositing an electrically insulating material further comprises performing a bumpless build-up layer process to embed metal features within the electrically insulating material configured to route I/O signals through the electrically insulating material.

20 . The method of claim 15 further comprising laser drilling vias in a surface of the electrically insulating material to reveal one or more of the first plurality of I/O interconnect structures or one or more of the second plurality of I/O interconnect structures.

Assignees

• Intel Corp

Inventors

• Mahajan Ravindranath V
• Nelson Christopher J
• Karhade Omkar G
• Eid Feras
• Deshpande Nitin A
• Liff Shawna M

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title