Semiconductor device with metal extrusion formation

Patent metadata

Field	Value
Publication number	US-9825120-B2
Application number	US-201615226186-A
Country	US
Kind code	B2
Filing date	Aug 2, 2016
Priority date	Jun 25, 2014
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

First claim

What is claimed:

1. A semiconductor structure comprising:
a Metal-insulator-metal (MIM) capacitor formed on a substrate, having a top plate, a bottom plate, and a dielectric layer; wherein:
the bottom plate includes an annealed first conductor on the substrate;
the dielectric layer includes an insulating layer on a portion of the annealed first conductor; and
the top plate includes a second conductor on the dielectric layer,
wherein the annealed first conductor includes one or more vertical extrusions in a top surface thereof at a position of the top surface that is free from having the dielectric layer thereover.

2. The semiconductor structure of claim 1 , wherein the annealed first conductor includes a substantially extrusion-free side surface subsequent to being annealed.

3. The semiconductor structure of claim 1 , wherein the annealed first conductor includes a portion of the annealed first conductor free of the dielectric layer and the top plate thereover.

4. The semiconductor structure of claim 1 , wherein the annealed first conductor comprises at least one layer comprising one or more of: Cu, Al, Al doped with Cu, W, Ti, and TiN prior to being annealed.

5. The semiconductor structure of claim 1 , wherein the dielectric layer comprises at least one of: SiC, Si 3 N 4 , Si02, and a low-K dielectric.

6. The semiconductor structure of claim 1 , wherein the annealed first conductor includes a layer of TiAl 3 subsequent to being annealed.

7. A semiconductor structure for an annealed metal wire comprising:
a semiconductor device formed on a substrate, having a conductor, and a dielectric layer; wherein:
the conductor is disposed on the substrate;
the dielectric layer includes an insulating layer disposed on the conductor,
wherein the conductor includes one or more vertical extrusions in a top surface thereof at a position of the top surface that is free from having the dielectric layer thereover.

8. The semiconductor structure of claim 7 , wherein the conductor includes a side surface being substantially free of extrusions.

Assignees

• IBM

Inventors

• Levy Max G
• Milo Gary L
• Thomas David C

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H01L21/32139

  Electricity · mapped topic

• H01L21/76895

  Electricity · mapped topic