Semiconductor device with metal extrusion formation

Patent metadata

Field	Value
Publication number	US-2016343797-A1
Application number	US-201615226185-A
Country	US
Kind code	A1
Filing date	Aug 2, 2016
Priority date	Jun 25, 2014
Publication date	Nov 24, 2016
Grant date	—

Abstract

Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

First claim

What is claimed:

1 . A method of fabricating a semiconductor structure comprising an annealed metal layer, the method comprising:
depositing a first conductive material on a semiconductor substrate; depositing a first dielectric material on the first conductive material; forming at least one opening in the first dielectric layer down to the first conductive material; and forming vertical extrusions in the first conductive material within the at least one opening in the first dielectric layer.

2 . The method of claim 1 , further comprising:
depositing a second conductive material on the first dielectric material, wherein the second conductive material is a top plate of a MIM capacitor; forming the top plate of the MIM capacitor comprising etching the second conductive material down to the first dielectric material; forming an insulating layer of the MIM capacitor comprising etching the first dielectric material down to the first conductive material; and forming a bottom plate of the MIM capacitor comprising etching a portion of the first dielectric material and a resulting exposed portion of the first conductive material down to the semiconductor substrate.

3 . The method of claim 1 , further comprising:
forming at least one opening in the first dielectric layer down to a portion of the first conductive material, wherein the portion of the first conductive material is a wire.

4 . The method of claim 1 , further comprising:
patterning an etch mask comprising at least one opening over the first dielectric layer and the first conductive material, wherein the etch mask comprises: at least one opening, wherein the first conductive material forms a wire, wherein the wire is greater than 5 microns wide; an edge of the at least one opening stops within a guard band distance from a perimeter of the wire; and a portion of the etch mask inside the perimeter of the wire stops within the guard band distance from a perimeter of an opening inside the wire.

5 . The method of claim 4 , wherein the etch mask further comprises:
a first portion of the etch mask inside the perimeter of the wire that covers at least one via land with an additional 0.75 micron width of etch mask; and a second portion of the etch mask inside the perimeter of the wire that is at least 0.4 micron wide.

6 . The method of claim 4 , wherein the guard band distance is 1 micron.

7 . The method of claim 1 , wherein the first conductive material forms a layer of TiAb after an annealing process.

8 . The method of claim 1 , wherein the first conductive material comprises at least one layer comprising one or more of: Cu, Al, Al doped with Cu, W, Ti, and TiN.

9 . The method of claim 1 , wherein the second conductive material comprises at least one layer comprising one or more of: Cu, Al, Al doped with Cu, W, Ti, and TiN.

10 . The method of claim 1 , wherein the first dielectric layer comprises at least one of: SiC, Si 3 N 4 , Si02, and a low-K dielectric.

11 . The method of claim 1 , further comprising:
depositing an inter-layer dielectric over the MIM capacitor; forming a first contact in the inter-layer dielectric, the first contact connecting the top plate of the MIM capacitor; forming a second contact in the inter-layer dielectric, the second contact connecting the bottom plate of the MIM capacitor; and forming a wiring layer over the first contact and the second contact.

Assignees

• IBM

Inventors

• Levy Max G
• Milo Gary L
• Thomas David C

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10D1/714

  having horizontal extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title