Semiconductor device and driving method thereof

Patent metadata

Field	Value
Publication number	US-9825037-B2
Application number	US-201615359873-A
Country	US
Kind code	B2
Filing date	Nov 23, 2016
Priority date	Aug 6, 2010
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

First claim

What is claimed is:

1. A semiconductor device comprising:
a line; and
a memory cell comprising a first transistor, a second transistor and a capacitor,
wherein the first transistor is a p-channel transistor and comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region,
wherein a first insulating layer covers the first transistor,
wherein the first insulating layer is over the first channel formation region,
wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region over the first insulating layer,
wherein a second insulating layer is over the second gate electrode,
wherein the second insulating layer includes aluminum and oxygen,
wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to each other to form a node where charge is held,
wherein the line, one of the first source electrode and the first drain electrode, and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first channel formation region includes silicon, and
wherein the second channel formation region includes an oxide semiconductor.

2. The semiconductor device according to claim 1 , wherein the second transistor is provided so as to overlap with at least part of the first transistor.

3. The semiconductor device according to claim 1 , wherein an n-channel transistor is used as the second transistor.

4. A semiconductor device comprising:
a line; and
a memory cell comprising a first transistor, a second transistor and a capacitor,
wherein the first transistor is a p-channel transistor and comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region,
wherein a first insulating layer covers the first transistor,
wherein the first insulating layer is over the first channel formation region,
wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region over the first insulating layer,
wherein a second insulating layer is over the second gate electrode,
wherein the second insulating layer includes aluminum and oxygen,
wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to each other to form a node where charge is held,
wherein the line, one of the first source electrode and the first drain electrode, and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first channel formation region includes silicon,
wherein the second channel formation region includes an oxide semiconductor, and
wherein an off-state current per micrometer of a channel width of the second transistor at room temperature is lower than or equal to 100 zA.

5. The semiconductor device according to claim 4 , wherein the second transistor is provided so as to overlap with at least part of the first transistor.

6. The semiconductor device according to claim 4 , wherein an n-channel transistor is used as the second transistor.

7. A semiconductor device comprising:
a line; and
a memory cell comprising a first transistor, a second transistor and a capacitor,
wherein the first transistor is a p-channel transistor and comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region,
wherein a first insulating layer covers the first transistor,
wherein the first insulating layer is over the first channel formation region,
wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region over the first insulating layer,
wherein a second insulating layer is over the second gate electrode,
wherein the second insulating layer includes aluminum and oxygen,
wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to each other to form a node where charge is held,
wherein the line, one of the first source electrode and the first drain electrode, and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first channel formation region includes silicon,
wherein the second channel formation region includes an oxide semiconductor,
wherein the semiconductor device implements a circuit diagram, and
wherein one of the first source electrode and the first drain electrode, and the other of the second source electrode and the second drain electrode are directly connected to each other in the circuit diagram.

8. The semiconductor device according to claim 7 , wherein the second transistor is provided so as to overlap with at least part of the first transistor.

9. The semiconductor device according to claim 7 , wherein an n-channel transistor is used as the second transistor.

Assignees

• Semiconductor Energy Lab

Inventors

• Inoue Hiroki
• Kato Kiyoshi
• Matsuzaki Takanori
• Nagatsuka Shuhei

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/202

  characterised by the semiconductor materials · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title