Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-8946703-B2
Application number	US-201414260598-A
Country	US
Kind code	B2
Filing date	Apr 24, 2014
Priority date	Aug 8, 2008
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

First claim

What is claimed is:

1. A semiconductor device comprising:
an insulating layer comprising silicon and excessive oxygen;
an oxide semiconductor layer in contact with the insulating layer, the oxide semiconductor layer including a channel formation region;
a gate electrode adjacent to the oxide semiconductor layer;
a first n-type conductivity region;
a second n-type conductivity region;
a source electrode comprising a first metal layer over the first n-type conductivity region, wherein the source electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the first n-type conductivity region; and
a drain electrode comprising a second metal layer over the second n-type conductivity region, wherein the drain electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the second n-type conductivity region.

2. The semiconductor device according to claim 1 ,
wherein the first n-type conductivity region is a layer formed over the oxide semiconductor layer, and
wherein the second n-type conductivity region is a layer formed over the oxide semiconductor layer.

3. The semiconductor device according to claims 1 ,
wherein a thickness of the first n-type conductivity region is 2 nm to 100 nm, and
wherein a thickness of the second n-type conductivity region is 2 nm to 100 nm.

4. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer comprises indium.

5. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

6. The semiconductor device according to claim 1 ,
wherein the insulating layer is located below the oxide semiconductor layer.

7. The semiconductor device according to claim 1 ,
wherein the first metal layer comprises titanium, and
wherein the second metal layer comprises titanium.

8. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

9. The semiconductor device according to claim 1 ,
wherein a carrier concentration in the first n-type conductivity region is higher than a carrier concentration in the oxide semiconductor layer, and
wherein a carrier concentration in the second n-type conductivity region is higher than the carrier concentration in the oxide semiconductor layer.

10. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer comprises excessive oxygen.

11. The semiconductor device according to claim 1 ,
wherein the first n-type conductivity region comprises indium, zinc, gallium and oxygen, and
wherein the second n-type conductivity region comprises indium, zinc, gallium and oxygen.

12. A semiconductor device comprising:
a gate electrode;
an insulating layer over the gate electrode, the insulating layer comprising silicon and excessive oxygen;
an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer including a channel formation region and being in contact with the insulating layer; and
a channel protective layer over the oxide semiconductor layer.

13. The semiconductor device according to claim 12 ,
wherein the oxide semiconductor layer comprises indium.

14. The semiconductor device according to claim 12 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

15. The semiconductor device according to claim 12 ,
wherein the insulating layer is located between the gate electrode and the oxide semiconductor layer.

16. The semiconductor device according to claim 12 ,
wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

17. The semiconductor device according to claim 12 ,
wherein the channel protective layer comprises silicon and excessive oxygen.

18. A semiconductor device comprising:
an insulating layer comprising silicon and oxygen;
an oxide semiconductor layer in contact with the insulating layer, the oxide semiconductor layer including a channel formation region;
a gate electrode adjacent to the oxide semiconductor layer;
a first n-type conductivity region;
a second n-type conductivity region;
a source electrode comprising a first metal layer over the first n-type conductivity region, wherein the source electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the first n-type conductivity region; and
a drain electrode comprising a second metal layer over the second n-type conductivity region, wherein the drain electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the second n-type conductivity region,
wherein the oxide semiconductor layer contains excessive oxygen.

19. The semiconductor device according to claim 18 ,
wherein the first n-type conductivity region is a layer formed over the oxide semiconductor layer, and
wherein the second n-type conductivity region is a layer formed over the oxide semiconductor layer.

20. The semiconductor device according to claim 18 ,
wherein a thickness of the first n-type conductivity region is 2 nm to 100 nm, and
wherein a thickness of the second n-type conductivity region is 2 nm to 100 nm.

21. The semiconductor device according to claim 18 ,
wherein the oxide semiconductor layer comprises indium.

22. The semiconductor device according to claim 18 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

23. The semiconductor device according to claim 18 ,
wherein the insulating layer is located below the oxide semiconductor layer.

24. The semiconductor device according to claim 18 ,
wherein the first metal layer comprises titanium, and
wherein the second metal layer comprises titanium.

25. The semiconductor device according to claim 18 ,
wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

26. The semiconductor device according to claim 18 ,
wherein a carrier concentration in the first n-type conductivity region is higher than a carrier concentration in the oxide semiconductor layer, and
wherein a carrier concentration in the second n-type conductivity region is higher than the carrier concentration in the oxide semiconductor layer.

27. The semiconductor device according to claim 18 ,
wherein the first n-type conductivity region comprises indium, zinc, gallium and oxygen, and
wherein the second n-type conductivity region comprises indium, zinc, gallium and oxygen.

28. A semiconductor device comprising:
a gate electrode;
an insulating layer over the gate electrode, the insulating layer comprising silicon and oxygen;
an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer including a channel formation region and being in contact with the insulating layer; and
a channel protective layer over the oxide semiconductor layer,
wherein the oxide semiconductor layer contains excessive oxygen.

29. The semiconductor device according to claim 28 ,
wherein the oxide semiconductor layer comprises indium.

30. The semiconductor device according to claim 28 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

31. The semiconductor device according to claim 28 ,
wherein the

Assignees

• Semiconductor Energy Lab

Inventors

• Miyairi Hidekazu
• Akimoto Kengo
• Nakamura Yasuo

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P50/69

  using masks for semiconductor materials · CPC title