Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9236456-B2
Application number	US-201514712254-A
Country	US
Kind code	B2
Filing date	May 14, 2015
Priority date	Aug 8, 2008
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate electrode;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer;
a second conductive layer over the oxide semiconductor layer;
a first oxide between the oxide semiconductor layer and the first conductive layer, the first oxide including titanium; and
a second oxide between the oxide semiconductor layer and the second conductive layer, the second oxide including titanium,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region is in contact with the insulating layer, and
wherein a thickness of the second region is smaller than a thickness of the first region.

2. The semiconductor device according to claim 1 , wherein the gate electrode includes aluminum, chromium, titanium, tantalum, molybdenum, or copper.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.

4. The semiconductor device according to claim 1 , wherein each of the first oxide and the second oxide has n-type conductivity.

5. The semiconductor device according to claim 1 ,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.

6. The semiconductor device according to claim 1 , wherein the second gate insulating layer contains excessive oxygen.

7. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer contains excessive oxygen.

8. A semiconductor device comprising:
a gate electrode;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer;
a second conductive layer over the oxide semiconductor layer;
a first oxide between the oxide semiconductor layer and the first conductive layer, the first oxide including titanium; and
a second oxide between the oxide semiconductor layer and the second conductive layer, the second oxide including titanium,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region is in contact with the insulating layer, wherein a thickness of the second region is smaller than a thickness of the first region, and
wherein the gate electrode has a light-shielding property.

9. The semiconductor device according to claim 8 , wherein the gate electrode includes aluminum, chromium, titanium, tantalum, molybdenum, or copper.

10. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.

11. The semiconductor device according to claim 8 , wherein each of the first oxide and the second oxide has n-type conductivity.

12. The semiconductor device according to claim 8 ,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.

13. The semiconductor device according to claim 8 , wherein the second gate insulating layer contains excessive oxygen.

14. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer contains excessive oxygen.

15. A semiconductor device comprising:
a gate electrode;
a first gate insulating layer over the gate electrode, the first gate insulating layer including silicon and nitrogen;
a second gate insulating layer over the first gate insulating layer, the second gate insulating layer including silicon and oxygen;
an oxide semiconductor layer over and in direct contact with the second gate insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc;
an insulating layer over a channel formation region of the oxide semiconductor layer, the insulating layer including silicon and oxygen;
a first conductive layer over the oxide semiconductor layer;
a second conductive layer over the oxide semiconductor layer;
a first oxide between the oxide semiconductor layer and the first conductive layer, the first oxide including titanium; and
a second oxide between the oxide semiconductor layer and the second conductive layer, the second oxide including titanium,
wherein the oxide semiconductor layer includes a first region and a second region,
wherein the first region is in contact with the insulating layer,
wherein a thickness of the second region is smaller than a thickness of the first region,
wherein the gate electrode has a light-shielding property, and
wherein each of the first gate insulating layer and the second gate insulating layer has a light-transmitting property.

16. The semiconductor device according to claim 15 , wherein the gate electrode includes aluminum, chromium, titanium, tantalum, molybdenum, or copper.

17. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer is formed by using a target obtained by mixing indium oxide, gallium oxide, and zinc oxide and performing sintering of the mixture of indium oxide, gallium oxide, and zinc oxide.

18. The semiconductor device according to claim 15 , wherein each of the first oxide and the second oxide has n-type conductivity.

19. The semiconductor device according to claim 15 ,
wherein the insulating layer overlaps the gate electrode,
wherein the insulating layer does not overlap a region of the oxide semiconductor layer, and
wherein the region of the oxide semiconductor layer does not overlap the gate electrode.

20. The semiconductor device according to claim 15 , wherein the second gate insulating layer contains excessive oxygen.

21. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer contains excessive oxygen.

Assignees

• Semiconductor Energy Lab

Inventors

• Miyairi Hidekazu
• Akimoto Kengo
• Nakamura Yasuo

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P50/69

  using masks for semiconductor materials · CPC title