Semiconductor device and driving method thereof

Patent metadata

Field	Value
Publication number	US-9525051-B2
Application number	US-201514740688-A
Country	US
Kind code	B2
Filing date	Jun 16, 2015
Priority date	Aug 6, 2010
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor layer over an insulating surface, the oxide semiconductor layer including a channel formation region, the oxide semiconductor layer containing indium, tin and zinc;
implanting oxygen ions into the oxide semiconductor layer;
performing a first heat treatment on the oxide semiconductor layer in an atmosphere containing nitrogen;
performing a second heat treatment on the oxide semiconductor layer in an atmosphere containing oxygen so that the oxide semiconductor layer includes excess oxygen and the oxide semiconductor layer is capable of compensating an oxygen deficiency in the oxide semiconductor layer;
wherein the second heat treatment is performed after the first heat treatment.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising the steps of:
forming a gate electrode layer so that the oxide semiconductor layer and the gate electrode layer overlap each other;
forming a first insulating layer including the insulating surface between the gate electrode layer and the oxide semiconductor layer;
forming a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer; and
forming a second insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer,
wherein the oxide semiconductor layer is formed by sputtering method.

3. The method for manufacturing a semiconductor device, according to claim 2 ,
wherein the first insulating layer is in direct contact with the oxide semiconductor layer, and
wherein the first insulating layer includes a region where the proportion of oxygen is higher than that in the stoichiometric composition.

4. The method for manufacturing a semiconductor device, according to claim 1 , wherein a temperature of the first heat treatment is higher than or equal to 250° C. and lower than or equal to 750° C.

5. The method for manufacturing a semiconductor device, according to claim 1 , further comprising the steps of:
forming a p-channel transistor wherein a gate of the p-channel transistor is electrically connected to a transistor comprising the oxide semiconductor layer, and
forming a bit line electrically connected to one of a source and a drain of the transistor and one of a source and a drain of the p-channel transistor.

6. The method for manufacturing a semiconductor device, according to claim 5 , wherein a channel region of the p-channel transistor includes silicon.

7. The method for manufacturing a semiconductor device, according to claim 1 , further comprising the steps of:
forming a p-channel transistor wherein a gate of the p-channel transistor is electrically connected to a transistor comprising the oxide semiconductor layer,
forming a bit line electrically connected to one of a source and a drain of the transistor and one of a source and a drain of the p-channel transistor, and
forming a capacitor element wherein one electrode of the capacitor element is electrically connected to the gate of the p-channel transistor and the other of the source and the drain of the transistor.

8. The method for manufacturing a semiconductor device, according to claim 1 , further comprising the steps of:
forming a p-channel transistor wherein a gate of the p-channel transistor is electrically connected to a transistor comprising the oxide semiconductor layer, and
forming a bit line electrically connected to one of a source and a drain of the transistor and one of a source and a drain of the p-channel transistor.

9. The method for manufacturing a semiconductor device, according to claim 8 , wherein a channel region of the p-channel transistor includes silicon.

10. The method for manufacturing a semiconductor device, according to claim 1 , further comprising the steps of:
forming a p-channel transistor wherein a gate of the p-channel transistor is electrically connected to a transistor comprising the oxide semiconductor layer,
forming a bit line electrically connected to one of a source and a drain of the transistor and one of a source and a drain of the p-channel transistor, and
forming a capacitor element wherein one electrode of the capacitor element is electrically connected to the gate of the p-channel transistor and the other of the source and the drain of the transistor.

11. A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor layer over an insulating surface, the oxide semiconductor layer including a channel formation region, the oxide semiconductor layer containing indium, tin and zinc;
implanting oxygen ions into the oxide semiconductor layer;
performing a first heat treatment on the oxide semiconductor layer in an atmosphere containing nitrogen;
performing a second heat treatment on the oxide semiconductor layer in an atmosphere containing oxygen so that the oxide semiconductor layer includes excess oxygen and the oxide semiconductor layer is capable of compensating an oxygen deficiency in the oxide semiconductor layer; and
performing a oxygen doping into the oxide semiconductor layer,
wherein the second heat treatment is performed after the first heat treatment.

12. The method for manufacturing a semiconductor device according to claim 11 , further comprising the steps of:
forming a gate electrode layer so that the oxide semiconductor layer and the gate electrode layer overlap each other;
forming a first insulating layer including the insulating surface between the gate electrode layer and the oxide semiconductor layer;
forming a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer; and
forming a second insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer,
wherein the oxide semiconductor layer is formed by sputtering method.

13. The method for manufacturing a semiconductor device, according to claim 12 ,
wherein the first insulating layer is in direct contact with the oxide semiconductor layer, and
wherein the first insulating layer includes a region where the proportion of oxygen is higher than that in the stoichiometric composition.

14. The method for manufacturing a semiconductor device, according to claim 11 , wherein a temperature of the first heat treatment is higher than or equal to 250° C. and lower than or equal to 750° C.

15. The method for manufacturing a semiconductor device, according to claim 11 , wherein the step of the oxygen doping into the oxide semiconductor layer is performed using an ion implantation method or an ion doping method.

Assignees

• Semiconductor Energy Lab

Inventors

• Inoue Hiroki
• Kato Kiyoshi
• Matsuzaki Takanori
• Nagatsuka Shuhei

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/202

  characterised by the semiconductor materials · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title