PECVD process

US9816187B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9816187-B2
Application numberUS-201615278455-A
CountryUS
Kind codeB2
Filing dateSep 28, 2016
Priority dateOct 26, 2012
Publication dateNov 14, 2017
Grant dateNov 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor processing apparatus, comprising: a chamber with a side wall and a floor; a lid coupled to the side wall, and together with the side wall and floor defining an internal volume, the lid comprising: a gas distributor having a plurality of gas flow openings; and a metrology device that directs and receives light through one of the gas flow openings; and a substrate support disposed in the internal volume. 2. The apparatus of claim 1 , wherein the metrology device directs light toward the substrate support and receives light reflected from inside the internal volume. 3. The apparatus of claim 1 , wherein the lid further comprises a zoned plate having a gas flow opening aligned with a gas flow opening of the gas distributor, wherein the metrology device directs and receives light through the gas flow openings of the zoned plate and the gas distributor. 4. The apparatus of claim 3 , wherein the lid further comprises a second zoned plate and the metrology device includes a collimator that fits an opening in the second zoned plate. 5. The apparatus of claim 4 , wherein the collimator does not contact the second zoned plate when disposed in the opening of the second zoned plate. 6. The apparatus of claim 3 , further comprising an electrode between the gas distributor and the side wall. 7. The apparatus of claim 6 , wherein the electrode is coupled to a tuning circuit having a variable impedance. 8. The apparatus of claim 7 , wherein the tuning circuit comprises a variable capacitor. 9. The apparatus of claim 6 , wherein the lid further comprises a heater. 10. The apparatus of claim 9 , wherein the heater is disposed at a periphery of the gas distributor. 11. The apparatus of claim 10 , wherein the substrate support comprises a zoned heater. 12. A semiconductor processing apparatus, comprising: a chamber with a side wall and a floor; a lid coupled to the side wall, and together with the side wall and floor defining an internal volume, the lid comprising: a gas distributor having a plurality of gas flow openings; and a metrology device that directs and receives light through one of the gas flow openings; a substrate support disposed in the internal volume; and an electrode between the gas distributor and the side wall. 13. The apparatus of claim 12 , wherein the metrology device comprises a fiber optic and a collimator housing the fiber optic, and the collimator fits an opening formed in the lid. 14. The apparatus of claim 13 , wherein the lid comprises a first zoned plate and a second zoned plate, and the opening is formed in the second zoned plate. 15. The apparatus of claim 14 , wherein the collimator seats in the first zoned plate. 16. The apparatus of claim 15 , wherein the collimator does not contact the second zoned plate when disposed in the opening of the second zoned plate. 17. The apparatus of claim 16 , wherein the substrate support comprises a zoned heater. 18. The apparatus of claim 17 , wherein the electrode is coupled to a variable impedance source. 19. A semiconductor processing apparatus, comprising: a chamber with a side wall and a floor; a lid coupled to the side wall, and together with the side wall and floor defining an internal volume, the lid comprising: a gas distributor having a plurality of gas flow openings; and a metrology device that directs and receives light through one of the gas flow openings; a substrate support disposed in the internal volume; and an electrode between the gas distributor and the side wall, the electrode coupled to a variable impedance source. 20. The apparatus of claim 19 , wherein the lid comprises a first zoned plate and a second zoned plate, an opening is formed in the second zoned plate, the metrology device comprises a fiber optic and a collimator housing the fiber optic, and the collimator fits the opening in the second zoned plate.

Assignees

Inventors

Classifications

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • Process monitoring, e.g. flow or thickness monitoring · CPC title

  • Temperature monitoring · CPC title

  • using mechanical means, e.g. clamps or pinches · CPC title

  • Heated nozzles · CPC title

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Frequently asked questions

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What does patent US9816187B2 cover?
A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality …
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/0602. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).