Circuit and method for controlling charge injection in radio frequency switches

Patent metadata

Field	Value
Publication number	US-9397656-B2
Application number	US-201414257808-A
Country	US
Kind code	B2
Filing date	Apr 21, 2014
Priority date	Jul 11, 2005
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

First claim

What is claimed is:

1. A switch circuit, comprising:
(a) a plurality of switching transistors, each having a gate configured to be coupled to a gate control signal and a gate-controlled channel, coupled in series through their respective gate-controlled channels to selectively convey a signal from an input of the series coupled switching transistors to an output of the series coupled switching transistors, the series of switching transistors including:
(1) a plurality of resistively-isolated nodes, each resistively-isolated node located between a different pair of the switching transistors in series; and
(2) at least one non-resistively-isolated node located adjacent to one of the plurality of the switching transistors in series;

and
(b) a plurality of charge injection control transistors, each control transistor having a gate configured to be coupled to a charge injection control signal and a gate-controlled channel operatively coupled between a different one of the plurality of resistively-isolated nodes and the at least one non-resistively-isolated node to selectively communicate injected charge from the different one of the plurality of resistively-isolated nodes to the at least one non-resistively-isolated node;
wherein each control transistor selectively switches between an OFF-state and an ON-state in response to application of the charge injection control signal, and selectively controls communication of injection charge only while in the ON-state.

2. The switch circuit of claim 1 , wherein when the series of switching transistors are switched from an ON-state to an OFF-state, the control transistors are switched from the ON-state to the OFF-state in response to application of the control signal after a selected delay time interval.

3. The switch circuit of claim 1 , wherein each control transistor has a width Wc substantially smaller than a width Ws of an associated and corresponding switching transistor such that the capacitance between the gate and the channel of each control transistor is substantially smaller than the capacitance between the gate and the channel of the associated and corresponding switching transistor.

4. The switch circuit of claim 3 , wherein Wc is approximately 0.1 as large as Ws.

5. A method of controlling charge injection in a switch circuit, including:
(a) employing a plurality of switching transistors, each having a gate configured to be coupled to a gate control signal and a gate-controlled channel, and being coupled in series through their respective gate-controlled channels, to selectively convey a signal from an input of the series coupled switching transistors to an output of the series coupled switching transistors; the series of switching transistors including:
(1) a plurality of resistively-isolated nodes, each resistively-isolated node located between a different pair of the switching transistors in series; and
(2) at least one non-resistively-isolated node located adjacent to one of the plurality of the switching transistors in series;

(b) generating injected charge at the plurality of resistively-isolated nodes;
(c) operatively coupling one of a plurality of charge injection control transistors, each control transistor having a gate configured to be coupled to a charge injection control signal and a gate-controlled channel, between a different one of the plurality of resistively-isolated nodes and the at least one non-resistively-isolated node to selectively communicate injected charge from the different one of plurality of resistively-isolated nodes to the at least one non-resistively-isolated node; and
(d) selectively switching each control transistor between an OFF-state and an ON-state in response to application of the charge injection control signal, and selectively controlling communication of injection charge only while in the ON-state.

6. The method of claim 5 , further including:
(a) switching the series of switching transistors from an ON-state to an OFF-state; and
(b) switching the control transistors from the ON-state to the OFF-state in response to application of the control signal after a selected delay time interval after the series of switching transistors is switched to the OFF-state.

7. The method of claim 5 , wherein each control transistor has a width Wc substantially smaller than a width Ws of an associated and corresponding switching transistor such that the capacitance between the gate and the channel of each control transistor is substantially smaller than the capacitance between the gate and the channel of the associated and corresponding switching transistor.

8. The switch circuit of claim 7 , wherein Wc is approximately 0.1 as large as Ws.

9. A switch circuit, including:
(a) a plurality of switching transistors, each having a gate configured to be coupled to a gate control signal and a gate-controlled channel, coupled in series through their respective gate-controlled channels to selectively convey a signal from an input of the series coupled switching transistors to an output of the series coupled switching transistors; the series of switching transistors including:
(1) a plurality of gate resistors, wherein a gate of each switching transistor is connected to a corresponding one of the plurality of gate resistors, and wherein each gate resistor is connected to a control line that conveys a control signal to the gate of each corresponding switching transistor;
(2) a plurality of resistively-isolated nodes, each resistively-isolated node located between a different pair of the switching transistors in series; and
(3) at least one non-resistively-isolated node located adjacent to one of the plurality of the switching transistors in series;

(b) means for generating injected charge at the plurality of resistively-isolated nodes; and
(c) control transistor switching means, operatively coupled to the generating means, each control transistor switching means having a gate configured to be coupled to a charge injection control signal and a gate-controlled channel, for selectively communicating injected charge from the different one of plurality of resistively-isolated nodes to the at least one non-resistively-isolated node,
(d) wherein each control transistor switching means selectively switches between an OFF-state and an ON-state in response to application of the charge injection control signal, and selectively controls communication of injection charge only while in the ON-state.

10. The switch circuit of claim 9 , further including:
(a) means for switching the series of switching transistors from an ON-state to an OFF-state; and
(b) means for switching the control transistor switching means from the ON-state to the OFF-state in response to application of the control signal after a selected delay time interval after the series of switching transistors is switched to the OFF-state.

11. The switch circuit of claim 9 , wherein each control transistor switching means has a width Wc substantially smaller than a width Ws of an associated and corresponding switching transistor such that the capacitance between the gate and the channel of each control transistor switching means is substantially smaller than the capacitance between the gate and the channel of the associated and corresponding switching transistor.

12. The switch circuit of claim 11 , wherein Wc is approximately 0.1 as large as Ws.

13. The switch circuit of claim 1 , wherein the switching transistors are enhancement-mode n-channel MOSFETs.

14. The method of claim 5 , wherein the switching transistors are enhancement-mode n-channel MOSFETs.

15. The switch circuit of claim

Assignees

• Peregrine Semiconductor Corp

Inventors

• Dribinsky Alexander
• Kim Tae Youn
• Kelly Dylan J
• Brindle Christopher N

Classifications

• H03K17/6874

  in a symmetrical configuration · CPC title

• H03K17/689

  with galvanic isolation between the control circuit and the output circuit (H03K17/78 takes precedence) · CPC title

• H03K17/04

  Modifications for accelerating switching · CPC title

• H03K17/102 Primary

  in field-effect transistor switches · CPC title

• H03K17/284 Primary

  in field effect transistor switches · CPC title