Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction

Patent metadata

Field	Value
Publication number	US-9087899-B2
Application number	US-201414198315-A
Country	US
Kind code	B2
Filing date	Mar 5, 2014
Priority date	Jul 11, 2005
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

First claim

The invention claimed is:

1. An accumulated charge control (ACC) floating body metal-oxide-semiconductor field effect transistor (MOSFET) comprising:
a gate;
a drain;
a source;
a body, wherein the body comprises a gate modulated conductive channel between the source and the drain;
a gate oxide layer positioned between the gate and the body; and
an accumulated charge sink (ACS) region operatively coupled to the body, wherein the ACS region comprises an implant region disposed within or adjacent the body; wherein accumulated charge is present in the body of the floating body MOSFET when the MOSFET is biased to operate in an accumulated charge regime and wherein accumulated charge is removed or controlled by applying a bias voltage to the ACS region,
wherein the gate modulated conductive channel, source, and drain have carriers of identical polarity when the MOSFET is biased to operate in an on-state and wherein the MOSFET operates in the accumulated charge regime when the MOSFET is biased to operate in a off-state and when the accumulated charge has a polarity that is opposite to the polarity of the source, drain, and gate modulated conductive channel, and
wherein the MOSFET has an operational body to gate bias voltage and the ACS region has parasitic MOS capacitance turned on at a body to gate bias voltage threshold and wherein the implant region is doped with selected dopant materials and at selected dopant levels to provide that the parasitic MOS capacitance is turned on at a body to gate bias voltage threshold less than or greater than the operational body to gate bias voltage.

2. The ACC MOSFET according to claim 1 , wherein the gate modulated conductive channel comprises material doped with a first dopant and the ACS region comprises material doped with a second dopant, wherein the second dopant is selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

3. The ACC MOSFET according to claim 1 , wherein the gate modulated conductive channel comprises material doped with a dopant at a first doping level and the ACS region comprises material doped with the dopant at a second doping level, wherein the second doping level is selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

4. The ACC MOSFET according to claim 1 , wherein the gate modulated conductive channel comprises material doped with a first dopant at a first doping level and the ACS region comprises material doped with a second dopant at a second doping level, wherein the second dopant and second doping level are selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

5. The ACC MOSFET according to claim 1 , further comprising an electrical contact region, wherein the electrical contact region and the ACS region are coextensive.

6. The ACC MOSFET according to claim 1 , further comprising an electrical contact region positioned proximate to and in electrical contact with the ACS region, wherein the electrical contact region facilitates electrical coupling to the ACS region and wherein the electrical contact region comprises same material as material comprising the ACS region.

7. The ACC MOSFET according to claim 1 , further comprising an electrical contact region positioned proximate to and in electrical contact with the ACS region, wherein the electrical contact region facilitates electrical coupling to the ACS region and wherein the electrical contact region comprises different material from material comprising the ACS region.

8. The ACC MOSFET according to claim 7 , wherein the electrical contact region comprises metal.

9. The ACC MOSFET according to claim 1 , wherein the ACS region is electrically coupled to the gate.

10. The ACC MOSFET according to claim 1 , wherein the ACC MOSFET comprises an NMOSFET device, and wherein the accumulated charge comprises holes having “P” polarity.

11. The ACC MOSFET according to claim 10 , wherein the NMOSFET comprises an enhancement mode NMOSFET.

12. The ACC MOSFET according to claim 11 , wherein the NMOSFET comprises a depletion mode NMOSFET.

13. An accumulated charge control floating body MOSFET (ACC MOSFET) adapted to control charge accumulated in the body of the MOSFET when the MOSFET is biased to operate in an accumulated charge regime, comprising:
a) a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET is biased to operate in the accumulated charge regime when the MOSFET is operated in a non-conducting or near non-conducting state and charge accumulates within the body in a region proximate and underneath the gate oxide layer;
b) a first accumulated charge sink (ACS) region positioned proximate a first distal end of the floating body, wherein the first ACS region is in electrical communication with the floating body, and wherein, when the MOSFET is operated in the accumulated charge regime, a first ACS bias voltage (V ACS1 ) is applied to the first ACS region to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the first ACS region;
c) a second accumulated charge sink (ACS) region positioned proximate a second distal end of the floating body, wherein the second ACS region is in electrical communication with the floating body and wherein, when the MOSFET is operated in the accumulated charge regime, a second ACS bias voltage (V ACS2 ) is applied to the second ACS region to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the second ACS region;
d) a first electrical contact region positioned proximate to and in electrical communication with the first ACS region, wherein the electrical contact region facilitates electrical coupling to the first ACS region;
e) a second electrical contact region positioned proximate to and in electrical communication with the second ACS region, wherein the electrical contact region facilitates electrical coupling to the second ACS region; and
f) a structure electrically connecting the first electrical contact region with the second electrical contact region, wherein the structure providing the electrical connection between the first electrical contact region and the second electrical contact region cancels or mostly cancels parasitic capacitance between the floating body and the gate.

14. The ACC MOSFET according to claim 13 , wherein the electrical communication between the first electrical contact region and the second electrical contact region is provided by a path having a path impedance.

15. The ACC MOSFET according to claim 14 , wherein the first ACS region couples to the floating body at a first ACS impedance and the second ACS region couples to the floating body at a second ACS impedance and the path impedance is less than the first ACS impedance and the path impedance is less than the second ACS impedance.

16. The ACC MOSFET according to claim 15 , wherein the first ACS region couples to the floating body at a first ACS impedance and the second ACS couples to the floating body at a second ACS region impedance and the path impedance is greater than the first ACS impedance and the path impedance is greater than the second ACS impedance.

17. The ACC MOSFET according to claim 13 , wherein the ACC MOSFET has an operational body to gate bias voltage and the first ACS region and the second

Assignees

• Peregrine Semiconductor Corp

Inventors

• Brindle Christopher N
• Deng Jie
• Genc Alper
• Yang Chieh-Kai

Classifications

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D62/125

  Shapes of junctions between the regions · CPC title