Circuits and methods for eliminating reference spurs in fractional-N frequency synthesis

Patent metadata

Field	Value
Publication number	US-9768790-B2
Application number	US-201615151198-A
Country	US
Kind code	B2
Filing date	May 10, 2016
Priority date	Apr 26, 2012
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

First claim

What is claimed is:

1. A circuit for a frequency synthesizer of a wireless device, comprising:
a phase frequency detector configured to generate a first signal based on a reference signal and a feedback signal; and
a compensation circuit configured to generate a compensation signal based on the first signal, the compensation circuit including a charging circuit and a charge pump configured to generate a current signal to compensate for a phase difference between the reference signal and the feedback signal, the current signal modulated based on a combination of the first signal and a pulse signal including a plurality of pulses each having a substantially constant width and beginning at a corresponding edge of the reference signal, the charging circuit including a capacitance element, a charging switch configured to facilitate charging of the capacitance element in response to the first signal, and a drain switch configured to facilitate draining of the charge in the capacitance element.

2. The circuit of claim 1 wherein the compensation circuit further includes a voltage-to-current converter configured to generate a control signal in response to a voltage of the capacitance element, the charge pump configured to generate the current signal based on the control signal from the voltage-to-current converter.

3. The circuit of claim 1 wherein the compensation circuit further includes a loop filter configured to receive the current signal and generate a corresponding voltage signal, the voltage signal being provided to a voltage-controlled oscillator in communication with the compensation circuit.

4. The circuit of claim 1 wherein the current signal has a pulse with a substantially constant width and an amplitude representative of the phase difference.

5. The circuit of claim 1 wherein the phase frequency detector is configured to generate an up signal or a down signal as the first signal, the up signal being generated when a phase of the reference signal leads a phase of the feedback signal, the down signal being generated when the phase of the reference signal lags behind the phase of the feedback signal.

6. The circuit of claim 5 wherein the charge pump includes a first current source configured to generate a positive current as the current signal for the up signal and a second current source configured to generate a negative current as the current signal for the down signal.

7. The circuit of claim 5 wherein the compensation circuit further includes a first switch in communication with a first current source configured to generate a positive current as the current signal for the up signal and a second switch in communication with a second current source configured to generate a negative current as the current signal for the down signal, the first and second switches configured to be controlled to provide a modulation of the current signal.

8. The circuit of claim 7 wherein the compensation circuit further includes a first switch configured to cause a positive current to be generated as the current signal and a second switch configured to cause a negative current to be generated as the current signal, the first switch or the second switch being engaged only when the capacitance element has a substantially full charge.

9. The circuit of claim 5 wherein the compensation circuit further includes a first switch configured to cause a positive current to be generated as the current signal and a second switch configured to cause a negative current to be generated as the current signal, the charging switch not being engaged if either of the first switch and the second switch is engaged.

10. The circuit of claim 5 wherein the compensation circuit further includes a first control block in communication with a first switch and a second control block in communication with a second switch, the first control block configured to generate a first enable pulse for the first switch based on a combination of the up signal and the pulse signal, the second control block configured to generate a second enable pulse for the second switch based on a combination of the down signal and the pulse signal.

11. The circuit of claim 5 wherein the compensation circuit further includes a first control block configured to generate a first enable signal based on the pulse signal and a first internal signal that goes high at a rising edge of the up signal and low at a falling edge of the pulse signal and a second control block configured to generate a second enable signal based on the pulse signal and a second internal signal that goes high at a rising edge of the down signal and low at the falling edge of the pulse signal.

12. The circuit of claim 5 wherein each one of the plurality of pulses of the pulse signal goes high at a corresponding falling edge of the reference signal.

13. The circuit of claim 1 further comprising a voltage-controlled oscillator in communication with the compensation circuit, the voltage-controlled oscillator configured to generate an output signal based on the compensation signal.

14. The circuit of claim 13 further comprising a divider circuit in communication with the voltage-controlled oscillator and the phase frequency detector, the divider circuit configured to receive the output signal from the voltage-controlled oscillator and generate an updated version of the feedback signal.

15. The circuit of claim 14 further comprising a sigma delta modulator in communication with the divider circuit to form a loop, the loop configured to allow the output signal to have an output frequency that is a non-integer multiple of a frequency of the reference signal.

16. The circuit of claim 1 wherein the circuit is a Frac-N phase-locked loop circuit.

17. A method for operating a frequency synthesizer of a wireless device, comprising:
generating a first signal based on a reference signal and a feedback signal; and
with a compensation circuit including (i) a charging circuit including a capacitance element, a charging switch configured to facilitate charging of the capacitance element in response to the first signal, and a drain switch configured to facilitate draining of the charge in the capacitance element and (ii) a charge pump configured to generate a current signal to compensate for a phase difference between the reference signal and the feedback signal, the current signal modulated based on a combination of the first signal and a pulse signal including a plurality of pulses each having a substantially constant width and beginning at a corresponding edge of the reference signal, generating a compensation signal based on the generated first signal.

18. A wireless communication device, comprising:
an antenna configured to facilitate reception of a radio-frequency signal;
a receiver in communication with the antenna, the receiver configured to process the radio-frequency signal; and
a frequency synthesizer circuit in communication with the receiver, the frequency synthesizer circuit including a phase frequency detector configured to generate a first signal based on a reference signal and a feedback signal, the frequency synthesizer circuit further including a compensation circuit configured to generate a compensation signal based on the first signal, the compensation circuit including a charging circuit and a charge pump configured to generate a current signal to compensate for a phase difference between the reference signal and the feedback signal, the current signal modulated based on a combination of the first signal and a pulse signal including a plurality of pulses each h

Assignees

• Skyworks Solutions Inc

Inventors

• Namdar-Mehdiabadi Ardeshir
• Frenette Darren Roger
• Rogers John William Mitchell

Classifications

• H03L7/0898

  the source or sink current values being variable (H03L7/0896 takes precedence) · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/1978

  using a cycle or pulse removing circuit · CPC title

• H04W88/02

  Terminal devices · CPC title

• H04L7/0045

  Correction by a latch cascade · CPC title