Circuits and methods for eliminating reference spurs in fractional-N frequency synthesis

Patent metadata

Field	Value
Publication number	US-9362925-B2
Application number	US-201514718677-A
Country	US
Kind code	B2
Filing date	May 21, 2015
Priority date	Apr 26, 2012
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

First claim

What is claimed is:

1. A circuit comprising:
a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal, the PFD further configured to generate a first signal based on the reference signal and the feedback signal; and
a compensation circuit configured to receive the first signal, the compensation circuit including a charging circuit, a charge pump, and a voltage-to-current converter positioned between the charging circuit and the charge pump, the charging circuit including a capacitance element, a charging switch configured to facilitate charging of the capacitance element in response to the first signal, and a drain switch configured to facilitate draining of the charge in the capacitance element, the compensation circuit further configured to generate a compensation signal based on the received first signal.

2. The circuit of claim 1 wherein the charge pump is configured to receive the first signal and generate a current signal to compensate for a phase difference between the reference signal and the feedback signal.

3. The circuit of claim 2 wherein the compensation circuit further includes a loop filter configured to receive the current signal and generate a corresponding voltage signal, the voltage signal being provided to a voltage controlled oscillator (VCO) in communication with the compensation circuit.

4. The circuit of claim 2 wherein the compensation signal includes the current signal having a pulse with a substantially constant width and an amplitude representative of the phase difference.

5. The circuit of claim 2 wherein the compensation circuit further includes a first switch configured to cause a positive current to be generated as the current signal and a second switch configured to cause a negative current to be generated as the current signal, the charging switch not being engaged if either of the first switch and the second switch is engaged.

6. The circuit of claim 1 wherein the PFD is configured to generate an up signal or a down (dn) signal as the first signal, the up signal being generated when a phase of the reference signal leads a phase of the feedback signal, the dn signal being generated when a phase of the reference signal lags a phase of the feedback signal.

7. The circuit of claim 6 wherein the charge pump includes a first current source configured to generate a positive current as a current signal for the up signal and a second current source configured to generate a negative current as the current signal for the dn signal.

8. The circuit of claim 6 wherein the compensation circuit further includes a first switch in communication with a first current source configured to generate a positive current as a current signal for the up signal and a second switch in communication with a second current source configured to generate a negative current as the current signal for the dn signal, the first and second switches configured to be controlled to provide a modulation of the current signal.

9. The circuit of claim 1 further comprising a voltage-controlled oscillator (VCO) in communication with the compensation circuit and a divider circuit in communication with the VCO and the PFD, the VCO configured to generate an output signal based on the compensation signal, the divider circuit configured to receive the output signal from the VCO and generate an updated version of the feedback signal.

10. The circuit of claim 9 further comprising a sigma delta modulator (SDM) in communication with the divider circuit to form a loop, the loop being configured to allow the output signal to have an output frequency that is a non-integer multiple of the, frequency of the reference signal.

11. The circuit of claim 1 wherein the circuit is a Frac-N phase-locked loop (PLL) circuit.

12. A circuit comprising:
a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal, the PFD further configured to generate a first signal based on the reference signal and the feedback signal; and
a compensation circuit configured to receive the first signal, the compensation circuit including a charging circuit, a charge pump, and a voltage-to-current converter positioned between the charging circuit and the charge pump, the voltage-to-current converter configured to generate a control signal in response to a voltage of a capacitance element of the charging circuit, the charge pump configured to receive the first signal and generate, based on the control signal from the voltage-to-current converter, a current signal to compensate for a phase difference between the reference signal and the feedback signal, the compensation circuit further configured to generate a compensation signal based on the received first signal.

13. A circuit comprising:
a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal, the PFD further configured to generate an up signal or a down (dn) signal based on the reference signal and the feedback signal, the up signal being generated when a phase of the reference signal leads a phase of the feedback signal, the dn signal being generated when a phase of the reference signal lags a phase of the feedback signal; and
a compensation circuit configured to receive the first signal, the compensation circuit including a charging circuit, a charge pump, and a voltage-to-current converter positioned between the charging circuit and the charge pump, the charge pump configured to receive the first signal and generate a current signal to compensate for a phase difference between the reference signal and the feedback signal, the current signal being modulated based on a combination of the up signal and a pulse signal or a combination of the dn signal and the pulse signal.

14. A circuit comprising:
a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal, the PFD further configured to generate an up signal or a down (dn) signal based on the reference signal and the feedback signal, the up signal being generated when a phase of the reference signal leads a phase of the feedback signal, the dn signal being generated when a phase of the reference signal lags a phase of the feedback signal; and
a compensation circuit configured to receive the first signal, the compensation circuit including a charging circuit including a capacitance element, a charge pump, and a voltage-to-current converter positioned between the charging circuit and the charge pump, the charge pump configured to receive the first signal and generate a current signal to compensate for a phase difference between the reference signal and the feedback signal, the compensation circuit further including a first switch configured to cause a positive current to be generated as the current signal and a second switch configured to cause a negative current to be generated as the current signal, the first switch or the second switch being engaged only when the capacitance element has a substantially full charge.

15. A circuit comprising:
a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal, the PFD further configured to generate an up signal or a down (dn) signal based on the reference signal and the feedback signal, the up signal being generated when a phase of the reference signal leads a phase of the feedback signal, the dn signal being generated when a phase of the reference signal lags a phase of the feedback signal; and
a compensation circuit configured to receive the first signal, the compensation circuit including a charging circuit, a charge pump, and a voltage-to-current

Assignees

• Skyworks Solutions Inc

Inventors

• Namdar-Mehdiabadi Ardeshir
• Frenette Darren Roger
• Rogers John William Mitchell

Classifications

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0898

  the source or sink current values being variable (H03L7/0896 takes precedence) · CPC title

• H03L7/1978

  using a cycle or pulse removing circuit · CPC title

• H03L7/0895 Primary

  Details of the current generators (H03L7/0893 takes precedence) · CPC title