Autonomous power supply

Patent metadata

Field	Value
Publication number	US-2016126784-A1
Application number	US-201414530189-A
Country	US
Kind code	A1
Filing date	Oct 31, 2014
Priority date	Oct 31, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

Aspects of the present disclosure are directed to providing power from two or more power sources. As may be implemented in accordance with one or more embodiments, a switching circuit includes a switching transistor connected between a backup power supply and both a primary power supply and an internal power rail. When power is provided via the primary power supply, the switching circuit operates in a blocking state in which back current is prevented from flowing to the backup power supply while the primary power supply couples power to the internal power rail. When the primary power supply is disconnected or interrupted, a voltage coupled to a gate/control terminal of the switching circuit drops and the switching circuit automatically switches to another state in which the internal power rail is powered by the backup power supply.

First claim

What is claimed is:

1 . An apparatus comprising:
an internal power rail configured and arranged to provide power to circuits in the apparatus; and a switching circuit including a switching transistor having a first source/drain region connected to a primary power supply circuit and to the internal power rail, having a second source/drain region connected to a backup power supply circuit, and having a control terminal coupled to the primary power supply circuit, the switching transistor being configured and arranged with the primary power supply circuit and with the backup power supply circuit to
respond to power provided via the primary power supply circuit, by automatically switching to a blocking state in which back current is prevented from flowing from the primary power supply circuit to the backup power supply circuit while the primary power supply circuit couples power to the internal power rail, and
respond to a voltage coupled to the control terminal via the primary power supply circuit and to a voltage on the primary power supply being smaller than a voltage on the backup power supply circuit, by automatically switching to another state in which the internal power rail is connected for providing power from the backup power supply circuit to the internal power rail.

2 . The apparatus of claim 1 , further including a charge pump configured and arranged to use power provided by the primary power supply circuit to operate the switching transistor in an OFF state by applying the voltage to the control terminal in the blocking state.

3 . The apparatus of claim 2 , wherein the charge pump is configured and arranged to cease applying the voltage to the control terminal in response to power dropping on the primary power supply circuit, and wherein the switching transistor is configured and arranged to automatically switch to an ON state in response to the charge pump ceasing to apply the voltage.

4 . The apparatus of claim 3 , wherein
the primary power supply circuit includes an input port at which power is provided to the primary power supply circuit and a second transistor having a gate coupled to an output voltage of the charge pump and a source and drain connected between the input port and a node directly connected to both the power rail and the first source/drain region of the switching transistor, and the charge pump is configured and arranged to couple power from the input port to the internal power rail by using the power provided by the primary power supply circuit to operate the second transistor in an ON state while operating the switching transistor in the OFF state.

5 . The apparatus of claim 4 , wherein
the switching transistor is a PMOS transistor configured and arranged to operate in the OFF state in response to a voltage level provided to a gate of the PMOS transistor by the charge pump and to operate in the ON state in response to the charge pump ceasing to provide the voltage level to the gate of the PMOS transistor, and the second transistor is an NMOS transistor configured and arranged to operate in the ON state in response to a voltage level provided to a gate of the NMOS transistor by the charge pump and to operate in the OFF state in response to the charge pump ceasing to provide the voltage level to the gate of the NMOS transistor.

6 . The apparatus of claim 5 , wherein the primary power supply circuit further includes a resistor circuit coupled to the second transistor and to the charge pump, and configured and arranged to mitigate back current flow from the internal power rail to the input port by discharging voltage from the gate of the second transistor in response to power provided on the input port transitioning toward 0V.

7 . The apparatus of claim 6 , wherein the primary power supply circuit further includes a capacitor circuit coupled to the second transistor and to the charge pump in parallel with the resistor circuit, and configured and arranged to reduce the coupling of voltage fluctuations from the input port to the gate of the second transistor.

8 . The apparatus of claim 5 , wherein the primary power supply circuit further includes a capacitor circuit coupled to the second transistor and to the charge pump, and configured and arranged to reduce the coupling of voltage fluctuations from the input port to the gate of the second transistor.

9 . The apparatus of claim 1 , wherein the primary power supply circuit includes an input transistor connected between a primary power supply port and the internal power rail, further including a voltage supply connected to respective control terminals of the transistors, the voltage supply being configured and arranged to
in response to power provided to the primary power supply port at a first level for powering the internal power rail, drive the input transistor in an ON state and drive the switching transistor in an OFF state, and in response to power provided to the primary power supply port at a second level that is below a threshold power for the internal power rail, drive the input transistor in an OFF state and drive the switching transistor in an ON state.

10 . The apparatus of claim 1 ,
further including a voltage supply connected to the control terminal of the switching transistor and powered via the primary power supply circuit, and wherein the switching transistor includes a channel connected to the internal power rail, and the control terminal of the switching transistor is responsive to the voltage supply by operating in an OFF state in which the back current is prevented from flowing in response to the voltage supply being powered, and by operating in an ON state and connecting the backup power supply circuit to the internal power rail when the voltage on the primary power supply circuit drops below a predefined threshold voltage.

11 . The apparatus of claim 1 ,
further including a voltage supply connected to the control terminal of the switching transistor and powered via the primary power supply circuit, wherein the switching transistor includes a channel connected to the internal power rail, and the control terminal of the switching transistor is responsive to the voltage supply by operating in an OFF state in which the back current is prevented from flowing in response to the voltage supply being powered, and by operating in an ON state and connecting the backup power supply circuit to the internal power rail when the voltage on the primary power supply circuit drops below a voltage level provided to the switching transistor by the backup power supply circuit.

12 . The apparatus of claim 1 , wherein the switching transistor is a P channel transistor configured and arranged to operate in an OFF state in response to a gate voltage provided by a power supply, and to transition to an ON state in response to the power supply ceasing to provide the gate voltage.

13 . The apparatus of claim 1 , wherein the primary power supply circuit further includes
a second transistor having a source and drain connected between an input port and a node directly connected to both the internal power rail and the first source/drain region of the switching transistor a resistor circuit coupled to a gate of the second transistor and configured and arranged to mitigate back current flow from the internal power rail to the input port by discharging voltage from the gate of the second transistor in response to power provided on the input port transitioning toward 0V, and a capacitor circuit coupled to the gate of the second transistor in parallel with the resistor circuit, and configured and arranged to reduce the coupling of voltage fluctuations from the i

Assignees

• Nxp Bv

Inventors

• Vemula Madan

Classifications

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02J9/061 Primary

  for DC powered loads · CPC title

• H02M7/217

  using semiconductor devices only · CPC title

• H03L7/0895

  Details of the current generators (H03L7/0893 takes precedence) · CPC title

• H02M7/538

  in a push-pull configuration (H02M7/5375 takes precedence {; with oscillating arrangements H02M7/53832, H02M7/53846}) · CPC title