Circuits and methods for eliminating reference spurs in fractional-n frequency synthesis

Patent metadata

Field	Value
Publication number	US-2016359494-A1
Application number	US-201615151198-A
Country	US
Kind code	A1
Filing date	May 10, 2016
Priority date	Apr 26, 2012
Publication date	Dec 8, 2016
Grant date	—

Abstract

Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

First claim

1 . (canceled)

2 . A circuit for a frequency synthesizer of a wireless device, comprising:
a phase frequency detector (PFD) configured to generate a first signal based on a reference signal and a feedback signal; and a compensation circuit configured to generate a compensation signal based on the first signal, the compensation circuit including a charging circuit, the charging circuit including a capacitance element, a charging switch configured to facilitate charging of the capacitance element in response to the first signal, and a drain switch configured to facilitate draining of the charge in the capacitance element.

3 . The circuit of claim 2 wherein the compensation circuit further includes a charge pump configured to generate a current signal to compensate for a phase difference between the reference signal and the feedback signal.

4 . The circuit of claim 3 wherein the compensation circuit further includes a voltage-to-current converter configured to generate a control signal in response to a voltage of the capacitance element, the charge pump configured to generate the current signal based on the control signal from the voltage-to-current converter.

5 . The circuit of claim 3 wherein the compensation circuit further includes a loop filter configured to receive the current signal and generate a corresponding voltage signal, the voltage signal being provided to a voltage controlled oscillator (VCO) in communication with the compensation circuit.

6 . The circuit of claim 3 wherein the compensation signal includes the current signal having a pulse with a substantially constant width and an amplitude representative of the phase difference.

7 . The circuit of claim 3 wherein the PFD is configured to generate an up signal or a down (dn) signal as the first signal, the up signal being generated when a phase of the reference signal leads a phase of the feedback signal, the dn signal being generated when a phase of the reference signal lags a phase of the feedback signal.

8 . The circuit of claim 7 wherein the charge pump includes a first current source configured to generate a positive current as the current signal for the up signal and a second current source configured to generate a negative current as the current signal for the dn signal.

9 . The circuit of claim 7 wherein the current signal is modulated based on a combination of the up signal and a pulse signal or a combination of the dn signal and the pulse signal.

10 . The circuit of claim 7 wherein the compensation circuit further includes a first switch in communication with a first current source configured to generate a positive current as the current signal for the up signal and a second switch in communication with a second current source configured to generate a negative current as the current signal for the dn signal, the first and second switches configured to be controlled to provide a modulation of the current signal.

11 . The circuit of claim 7 wherein the compensation circuit further includes a first switch configured to cause a positive current to be generated as the current signal and a second switch configured to cause a negative current to be generated as the current signal, the first switch or the second switch being engaged only when the capacitance element has a substantially full charge.

12 . The circuit of claim 7 wherein the compensation circuit further includes a first switch configured to cause a positive current to be generated as the current signal and a second switch configured to cause a negative current to be generated as the current signal, the charging switch not being engaged if either of the first switch and the second switch is engaged.

13 . The circuit of claim 7 wherein the compensation circuit further includes a first control block in communication with a first switch and a second control block in communication with a second switch, the first control block configured to generate a first enable pulse for the first switch based on a combination of the up signal and a pulse signal, the second control block configured to generate a second enable pulse for the second switch based on a combination of the dn signal and the pulse signal.

14 . The circuit of claim 7 wherein the compensation circuit further includes a first control block configured to generate a first enable signal based on the pulse signal and a first internal signal that goes high with a rising edge of the up signal and low with a falling edge of the pulse signal and a second control block configured to generate a second enable signal based on the pulse signal and a second internal signal that goes high with a rising edge of the dn signal and low with the falling edge of the pulse signal.

15 . The circuit of claim 7 wherein the current signal is modulated based on a combination of the up signal and a pulse signal or a combination of the dn signal and the pulse signal, the pulse signal including a plurality of pulses, each pulse having a substantially constant width and going high with a falling edge of the reference signal.

16 . The circuit of claim 2 further comprising a voltage-controlled oscillator (VCO) in communication with the compensation circuit, the VCO configured to generate an output signal based on the compensation signal.

17 . The circuit of claim 16 further comprising a divider circuit in communication with the VCO and the PFD, the divider circuit configured to receive the output signal from the VCO and generate an updated version of the feedback signal.

18 . The circuit of claim 17 further comprising a sigma delta modulator (SDM) in communication with the divider circuit to form a loop, the loop being configured to allow the output signal to have an output frequency that is a non-integer multiple of the frequency of the reference signal.

19 . The circuit of claim 2 wherein the circuit is a Frac-N phase-locked loop (PLL) circuit.

20 . A method for operating a frequency synthesizer of a wireless device, comprising:
generating a first signal based on a reference signal and a feedback signal; and with a compensation circuit including a charging circuit including a capacitance element, a charging switch configured to facilitate charging of the capacitance element in response to the first signal, and a drain switch configured to facilitate draining of the charge in the capacitance element, generating a compensation signal based on the generated first signal.

21 . A wireless communication device, comprising:
an antenna configured to facilitate reception of a radio-frequency (RF) signal; a receiver in communication with the antenna, the receiver configured to process the RF signal; and a frequency synthesizer circuit in communication with the receiver, the frequency synthesizer circuit including a phase frequency detector (PFD) configured to generate a first signal based on a reference signal and a feedback signal, the frequency synthesizer circuit further including a compensation circuit configured to generate a compensation signal based on the first signal, the compensation circuit including a charging circuit including a capacitance element, a charging switch configured to facilitate charging of the capacitance element in response to the first signal, and a drain switch configured to facilitate draining of the charge in the capacitance element.

Assignees

• Skyworks Solutions Inc

Inventors

• Namdar-Mehdiabadi Ardeshir
• Frenette Darren Roger
• Rogers John William Mitchell

Classifications

• H04L7/0016

  correction of synchronization errors · CPC title

• H03L7/1974 Primary

  for fractional frequency division · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title