Filler insertion in circuit layout

Patent metadata

Field	Value
Publication number	US-9542521-B2
Application number	US-201414496774-A
Country	US
Kind code	B2
Filing date	Sep 25, 2014
Priority date	Sep 25, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells is disclosed. First, a set of filler classes, each filler class having a set of filler cells, is classified that are configured to fill the gaps depending on a design requirement. Then, a filler insertion pattern based on a required ratio is identified such that horizontal and vertical density of the set of filler classes in the circuit layout are as per the required ratio and the cell row of the circuit layout has at least one filler cell from each of the set of filler classes.

First claim

What is claimed is:

1. A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells, comprising:
classifying a set of filler classes including a decap, a standard cell filler and an always-on decap, each filler class having a set of filler cells, that are configured to fill the gaps depending on a design requirement;
identifying a required ratio of the set of filler classes that fills the gaps in the circuit layout; and
identifying a filler insertion pattern based on the required ratio such that horizontal and vertical density of the set of filler classes in the circuit layout are as per the required ratio and the cell row of the circuit layout has at least one filler cell from each of the set of filler classes;
wherein the set of filler classes and the standard cells are fabricated on a semiconductor substrate; and
wherein identifying a required ratio of the set of filler classes comprises identifying the required ratio that is configurable as per the design requirement.

2. The method of claim 1 and further comprising inserting the set of filler classes according to the filler insertion pattern in the circuit layout.

3. The method of claim 1 , wherein identifying a filler insertion pattern based on the required ratio comprises identifying a filler insertion pattern such that the cell row has at least one filler cell from each of the set of filler classes.

4. The method of claim 3 , wherein the filler insertion pattern is identified such that an engineering change order is accommodated for the cell row and an IR robustness for the circuit layout is improved.

5. A semiconductor device having a circuit layout, the circuit layout comprising:
a plurality of cell rows of standard cells and gaps between the standard cells; and
a set of filler classes in the gaps, wherein a horizontal and a vertical density of the set of filler classes are the same in the circuit layout and each of the cell rows has one or more types of filler classes of the set of filler classes;
a required ratio of the set of filler classes that fills the gaps in the circuit layout;
wherein the set of filler classes and the standard cells are fabricated on a semiconductor substrate; and
wherein the required ratio of the set of filler classes is configurable.

6. The circuit layout of claim 5 , wherein the set of filler classes comprises at least one of a decap, a standard cell filler and an always-on decap.

7. The circuit layout of claim 5 , wherein the set of filler classes in the gaps is such that each of the cell rows has at least one standard cell and at least one decap.

8. A non-transitory computer readable medium, for use by a computer system, provided with a layout of a circuit for filler insertions in a circuit layout having a plurality of cell rows of standard cells and gaps between the standard cells, comprising:
a set of filler classes in the gaps, wherein a horizontal and a vertical density of the set of filler classes are the same in the circuit layout and each of the cell rows has one or more types of filler classes of the set of filler classes: a required ratio of the set of filler classes that fills the gaps in the circuit layout;
wherein the set of filler classes and the standard cells are fabricated on a semiconductor substrate; and
wherein the required ratio of the set of filler classes is configurable.

9. The non-transitory computer readable medium of claim 8 , wherein the set of filler classes comprises at least one of a decap, a standard cell filler and an always-on decap.

10. The non-transitory computer readable medium of claim 8 , wherein the set of filler classes in the gaps is such that each of the cell rows has at least one standard cell and at least one decap.

Assignees

• Texas Instruments Inc

Inventors

• Somayaji Ananth
• Modi Sourav
• Dewal Sani
• Ambikapathy Saravanan

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F2217/78

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic