Handheld electronic device
US-2025240363-A1 · Jul 24, 2025 · US
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Lee Sherry patents
Lee Sherry is listed as an inventor on 95 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lee Sherry |
| Total patents | 95 |
| First publication | Apr 18, 2017 |
| Latest publication | Jul 24, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Handheld electronic device
US-2025240360-A1 · Jul 24, 2025 · US
Handheld electronic device
US-12301744-B2 · May 13, 2025 · US
Handheld electronic device
US-11838432-B2 · Dec 5, 2023 · US
Handheld electronic device
US-2023221782-A1 · Jul 13, 2023 · US
Wireless charging systems for electronic devices
US-11165273-B2 · Nov 2, 2021 · US
Battery for an electronic device
US-D929317-S · Aug 31, 2021 · US
IC with test structures and e-beam pads embedded within a contiguous standard cell area
US-11107804-B1 · Aug 31, 2021 · US
IC with test structures and e-beam pads embedded within a contiguous standard cell area
US-11081476-B1 · Aug 3, 2021 · US
IC with test structures and e-beam pads embedded within a contiguous standard cell area
US-11081477-B1 · Aug 3, 2021 · US
Recent patents
Latest publications not already listed above.
IC with test structures and E-beam pads embedded within a contiguous standard cell area
US-11075194-B1 · Jul 27, 2021 · US
Handheld electronic device
US-2021168226-A1 · Jun 3, 2021 · US
IC with test structures and e-beam pads embedded within a contiguous standard cell area
US-11018126-B1 · May 25, 2021 · US
IC with test structures and E-beam pads embedded within a contiguous standard cell area
US-10978438-B1 · Apr 13, 2021 · US
Battery for an electronic device
US-D910545-S · Feb 16, 2021 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas
US-10854522-B1 · Dec 1, 2020 · US
IC with test structures embedded within a contiguous standard cell area
US-10777472-B1 · Sep 15, 2020 · US
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
US-10593604-B1 · Mar 17, 2020 · US
Wireless charging systems for electronic devices
US-2019363565-A1 · Nov 28, 2019 · US
Switched antenna assembly
US-10461429-B2 · Oct 29, 2019 · US
Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
US-10290552-B1 · May 14, 2019 · US
Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells
US-10269786-B1 · Apr 23, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas
US-10211112-B1 · Feb 19, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas
US-10211111-B1 · Feb 19, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas
US-10199289-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
US-10199294-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas
US-10199287-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areas
US-10199284-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas
US-10199285-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas
US-10199286-B1 · Feb 5, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Pdf Solutions Inc | 83 |
| Apple Inc | 12 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10P74/277 | 82 |
| G06F30/392 | 80 |
| H10D89/10 | 80 |
| G06F30/398 | 80 |
| H10P74/23 | 79 |