Use of layout analysis to enable efficient and effective random defect inspection using a vector-mode e-beam inspection machine
US-2025085234-A1 · Mar 13, 2025 · US
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Rauscher Markus patents
Rauscher Markus is listed as an inventor on 84 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Rauscher Markus |
| Total patents | 84 |
| First publication | Apr 18, 2017 |
| Latest publication | Mar 13, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
IC with test structures and e-beam pads embedded within a contiguous standard cell area
US-11107804-B1 · Aug 31, 2021 · US
IC with test structures and e-beam pads embedded within a contiguous standard cell area
US-11081476-B1 · Aug 3, 2021 · US
IC with test structures and e-beam pads embedded within a contiguous standard cell area
US-11081477-B1 · Aug 3, 2021 · US
IC with test structures and E-beam pads embedded within a contiguous standard cell area
US-11075194-B1 · Jul 27, 2021 · US
IC with test structures and e-beam pads embedded within a contiguous standard cell area
US-11018126-B1 · May 25, 2021 · US
IC with test structures and E-beam pads embedded within a contiguous standard cell area
US-10978438-B1 · Apr 13, 2021 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas
US-10854522-B1 · Dec 1, 2020 · US
IC with test structures embedded within a contiguous standard cell area
US-10777472-B1 · Sep 15, 2020 · US
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
US-10593604-B1 · Mar 17, 2020 · US
Recent patents
Latest publications not already listed above.
Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
US-10290552-B1 · May 14, 2019 · US
Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells
US-10269786-B1 · Apr 23, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas
US-10211112-B1 · Feb 19, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas
US-10211111-B1 · Feb 19, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas
US-10199289-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
US-10199294-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas
US-10199287-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areas
US-10199284-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas
US-10199285-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas
US-10199286-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
US-10199290-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage
US-10199283-B1 · Feb 5, 2019 · US
Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas
US-10199293-B1 · Feb 5, 2019 · US
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas
US-10199288-B1 · Feb 5, 2019 · US
Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
US-10109539-B1 · Oct 23, 2018 · US
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells
US-10096529-B1 · Oct 9, 2018 · US
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
US-10096530-B1 · Oct 9, 2018 · US
Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells
US-9984944-B1 · May 29, 2018 · US
Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens
US-9953889-B1 · Apr 24, 2018 · US
Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
US-9947601-B1 · Apr 17, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Pdf Solutions Inc | 84 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10P74/277 | 82 |
| G06F30/392 | 80 |
| H10D89/10 | 80 |
| G06F30/398 | 80 |
| H10P74/23 | 79 |